Load Register Instruction Short Circuiting via Register Aliasing
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Solution Overview
Problem
Existing methods for executing Load Register (LR) instructions in microprocessors require additional physical registers, issue queue entries, and fixed-point unit execution cycles, leading to inefficient resource utilization and delayed execution of subsequent instructions.
Innovation Solution
The method involves retaining the source data of the Load Register instruction in the original physical register while aliasing the architected source and target registers to the same physical register, and dynamically re-assigning free registers as needed for subsequent instructions, eliminating the need for data movement and reducing resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a Load Register instruction is executed to copy register contents, then data preservation is achieved, but additional physical registers, issue queue entries, and execution cycles are consumed
Solution Approach 1:
The patent merges the source register and target register mappings to the same physical register when executing Load Register instructions. Instead of allocating a separate physical register for the copied data, the system makes both architected registers alias to the same physical register, eliminating the need for additional physical registers and issue queue entries while maintaining data preservation functionality
2Reliability
If a Load Register instruction is executed to preserve data, then data availability for subsequent instructions is ensured, but execution of dependent instructions is delayed
Solution Approach 1:
The patent performs preliminary mapping setup where the physical register is allocated and both architected registers are mapped to it before the actual data copy operation. This preliminary action allows subsequent instructions to be issued immediately without waiting for the data copy to complete, as the data path is already established through the aliasing mechanism
3Reliability
If separate physical registers are assigned for source and target of Load Register instruction, then data copy is achieved, but register utilization efficiency decreases
Solution Approach 1:
The patent makes the physical register serve multiple functions by allowing two different architected registers to alias to the same physical register. This multi-functionality enables the single physical register to act as both the source and target for the Load Register instruction, improving register utilization efficiency while maintaining the data copy functionality through the aliasing mechanism
Data Source
AI summary
An apparatus and method for executing a Load Register instruction in which the source data of the Load Register instruction is retained in its original physical register while the architected target register is mapped to this same physical target register. In this state the two architected registers alias to one physical register. When the source register of the Load Address instruction is specified as the target address of a subsequent instruction, a free physical register is assigned to the Load Registers source register. And with this assignment the alias is thus broken. Similarly when the target register of the Load Address instruction is the target address of a subsequent instruction, a new physical register is assigned to the Load Registers target address. And with this assignment the alias is thus broken.