LRDIMM Memory Module Virtual Buffer Design
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Solution Overview
Problem
Memory modules of the LRDIMM type require a data buffer, which limits the number of memory devices that can be mounted on a printed circuit board and introduces latency in read and write operations due to the need for data to be read or written through the buffer.
Innovation Solution
A memory module operates as an LRDIMM type without a data buffer by using a device controller that communicates with a host device via a first interface and a memory device via a second interface, performing initialization and training operations in various modes to replicate the memory interface training, allowing the module to be recognized as having a virtual data buffer by the host.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a data buffer is mounted on the printed circuit board to operate as an LRDIMM type, then the memory module can be recognized as LRDIMM by the host, but the number of memory devices that can be mounted is limited and read/write latency increases
Solution Approach 1:
The patent creates a virtual data buffer through software simulation in the device controller, which copies the functionality of a physical data buffer without requiring actual hardware. The virtual buffer emulates LRDIMM behavior by managing data transfer timing and protocol compliance, allowing the system to achieve LRDIMM recognition while using direct memory device connections that can accommodate more devices.
Solution Approach 2:
The patent replaces the mechanical/physical data buffer hardware with a software-based virtual buffer implementation. Instead of using physical memory cells and buffer circuits on the printed circuit board, the device controller uses firmware to simulate buffer operations, thereby eliminating the need for physical buffer components and enabling direct connection to more memory devices.
2Adaptability or versatility
If a data buffer is mounted on the printed circuit board, then the memory module can operate as LRDIMM type, but read and write latency increases due to data passing through the buffer
Solution Approach 1:
The virtual data buffer copies only the essential control and timing functions of a physical buffer without the data storage and retrieval overhead. By simulating buffer behavior through software state machines and timing controllers, the system achieves protocol compliance while maintaining direct data paths that eliminate buffer access latency.
Solution Approach 2:
The patent extracts the essential buffer functionality (timing control, protocol management) from the physical data buffer hardware and relocates it to software in the device controller. This separation allows the removal of the physical buffer component entirely, eliminating the time penalty associated with data traversal through buffer memory while preserving the necessary control functions.
3Adaptability or versatility
If a data buffer is mounted on the printed circuit board, then the memory module can operate as LRDIMM type, but the area occupied on the printed circuit board increases
Solution Approach 1:
The patent uses software simulation to copy the functional behavior of a data buffer without requiring physical hardware implementation. The virtual buffer resides in the device controller's memory space and logic, eliminating the need for dedicated buffer circuitry, capacitors, and interconnect traces on the printed circuit board, thereby freeing up valuable board real estate.
Solution Approach 2:
The patent substitutes the mechanical/physical buffer hardware with a software-based implementation in the device controller. This replacement eliminates the need for physical buffer components, reducing the printed circuit board area required for buffer mounting while maintaining LRDIMM operational characteristics through firmware-controlled data management.
Data Source
AI summary
A memory module includes a device controller that communicates with a host device based on a first interface including a first clock signal, a first data signal, and a first data strobe signal and operates in one of a first operation mode or a second operation mode depending on an operation mode control value from the host device, and a memory device that communicates with the device controller based on a second interface including a second data signal and a second data strobe signal. The device controller includes a logic circuit that transmits a predetermined training result value to the host device depending on a training control value from the host device, when a training is performed on a third interface being a virtual interface recognized by the host device in the first operation mode.