Bridge Fault Detection in LSI Using Logical Threshold Analysis
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Solution Overview
Problem
Current bridge fault tests in semiconductor integrated circuits face challenges in detecting bridge faults due to increased IDDQ current values in high clock frequency LSIs, making it difficult to distinguish abnormal from fault-free conditions, and existing methods are inefficient in generating high-precision test patterns for large-scaled LSIs.
Innovation Solution
A fault list and test pattern generating apparatus that includes modules for generating electrical short information, logical threshold values, and extracting bridge fault information from the layout of semiconductor integrated circuits to create a bridge fault list and test patterns that detect bridge faults in adjacent wire pairs, considering voltage values and logical threshold values at shorted portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If IDDQ test is used to detect bridge faults, then bridge faults can be detected, but the increased IDDQ current values in high clock frequency LSIs make it difficult to distinguish abnormal from fault-free conditions
Solution Approach 1:
The patent replaces the electrical measurement-based IDDQ test with a logical simulation-based detection method. Instead of measuring actual current values, the system uses logical simulation to model bridge fault conditions and determine detectability based on logical relationships between signals, thereby avoiding the precision issues of electrical measurement in high-frequency circuits
Solution Approach 2:
The patent creates a logical copy or model of the circuit behavior rather than directly measuring the physical circuit. By simulating the logical behavior of signals and their relationships, the system can assess bridge fault detectability without being affected by the actual electrical characteristics that cause measurement precision problems
2Ease of manufacture
If simple bridge fault tests are used, then test implementation is straightforward, but detection precision is insufficient for recent large-scaled LSIs
Solution Approach 1:
The patent segments the bridge fault detection problem into multiple components: extracting bridge fault information from layout, determining driving and receiving cells, calculating logical threshold values, and evaluating detection credibility. This segmentation allows complex precision requirements to be met through systematic analysis of individual components rather than requiring complex overall test implementations
Solution Approach 2:
The patent performs preliminary analysis by extracting bridge fault information from the layout before actual testing. By pre-determining which cells are driving or receiving signals and calculating logical threshold values in advance, the system can accurately assess detection precision without requiring complex real-time test implementations
Data Source
AI summary
The test pattern generating apparatus contains a module configured to generate short information indicative of a relationship between a logical value of an input signal of a cell and a voltage of an electrically shorted portion assumed at an output terminal of the cell; a module configured to calculate a logical threshold value of the input terminal of the cell so as to generate logical threshold value information; a module configured to extract a bridge fault information from layout information of an LSI; a module configured to generate a bridge fault list including a bridge fault type based on the bridge fault information, the short information, and the logical threshold value information; and a module configured to generate a test pattern which detects bridge faults in an adjacent signal wire pair and a bridge fault type.