LSI Clock Tree Design Optimizing Skew and Power via H-Tree Segmentation
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Solution Overview
Problem
Existing clock tree design methods, such as CTS and H-tree, face challenges in optimizing the number of stages to minimize power consumption while maintaining low clock skew and uniform fan-out distribution, especially when leaves are not uniformly distributed across the LSI chip.
Innovation Solution
A method that divides leaves into groups to form local trees and uniformly places clock buffers with equal load through equal-length routing, iteratively refining the division until skew and fan-out constraints are met, optimizing the number of stages in the high-level clock tree.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CTS inserts a large number of clock buffers to reduce clock skew, then clock skew is reduced, but power consumption increases
Solution Approach 1:
The patent segments the clock tree into multiple stages, with each stage having a specific function. The first stage uses H-tree for uniform distribution, while subsequent stages use CTS for optimization. This segmentation allows each method to operate in its optimal range, reducing the total number of buffers needed while maintaining skew constraints.
Solution Approach 2:
The patent applies different clock tree synthesis methods to different regions and stages of the clock distribution network. H-tree is used in the first stage where uniform distribution is critical, while CTS is used in subsequent stages where local optimization is more effective. This local quality approach optimizes power consumption by applying the right method in the right place.
2Reliability
If H-tree places clock buffers with equal load and equal-length routing, then clock skew is theoretically zero, but the number of stages must be determined by the densest leaf region, causing excessive buffers in sparse regions and increased power consumption
Solution Approach 1:
The patent segments the clock tree into a first stage using H-tree and subsequent stages using CTS. This segmentation allows H-tree to establish a foundation with theoretically zero skew, while CTS optimizes the remaining stages to reduce buffer count in sparse regions, thereby reducing power consumption without compromising overall skew performance.
Solution Approach 2:
Instead of applying H-tree uniformly throughout the entire clock distribution network, the patent applies it only partially in the first stage. The remaining stages use CTS, which performs partial optimization. This partial application of H-tree avoids the excessive buffer placement in sparse regions while maintaining skew constraints where critical.
3Adaptability or versatility
If leaves are not uniformly distributed across the LSI chip, then routing length variation occurs, causing clock skew increase
Solution Approach 1:
The patent applies local quality by using CTS in subsequent stages after the initial H-tree stage. CTS can locally adjust buffer placement and routing to compensate for non-uniform leaf distribution, thereby maintaining skew constraints even when leaves are not uniformly distributed across the chip.
Solution Approach 2:
The patent introduces dynamics by allowing the clock tree structure to adapt through multi-stage synthesis. The first stage establishes a static H-tree framework, while subsequent CTS stages dynamically optimize the structure based on actual leaf distribution, routing constraints, and skew requirements, making the overall system adaptable to non-uniform layouts.
Data Source
AI summary
In an LSI design method of designing a clock tree that supplies a clock signal to a plurality of leaves from a clock supply point, when a high level clock tree is constituted by H-tree and a low level clock tree is formed by CTS, the number of stages of a high level clock tree is optimized without giving any constraint on the placement of a low level clock tree. The leaves are divided into a plurality of groups to form a low level local tree. A clock-supplied region including all leaves to be supplied with a clock is uniformly divided and for each divided region, a skew when a clock signal is supplied from an end of an H-tree to start points of a plurality of local trees included in that region is estimated. The clock-supplied region is more finely equally-divided to increase the number of stages of H-tree.