Controller LSI Low Power Mode SPI Flash Release

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Solution Overview

Problem

Controller LSIs face issues transitioning to low power consumption modes, leading to data volatilization in volatile memory, which prevents the release of peripheral devices from deep power down modes, causing operational deadlocks and inability to resume normal operations.

Innovation Solution

Incorporating a control unit within the controller LSI that transmits a release command irrespective of the peripheral device's mode, ensuring data integrity and enabling proper transition out of low power consumption modes, along with features like boot controllers and adaptable command codes for SPI communication standards.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the controller LSI transitions to low power consumption mode to reduce energy usage, then power consumption is reduced, but data stored in volatile memory is volatilized, preventing proper release of peripheral devices from deep power down mode

Engineering Contradiction:

Improvepower consumptionVSAvoiddata integrity

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The control unit checks the operation mode of the peripheral device before the controller LSI transitions to low power consumption mode. If the peripheral device is in deep power down mode, the control unit issues a release command in advance to ensure the device can be properly released even after data volatilization occurs in volatile memory.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The control unit continuously monitors the operation mode of the peripheral device and adjusts its behavior based on this feedback. When detecting that the peripheral device is in deep power down mode, the control unit triggers the release command mechanism to maintain proper device state management despite data loss in volatile memory.

Inventive Principle:

Principle #23Feedback

2Use of energy by stationary object

If the controller LSI enters deep power down mode to suspend power supply to CPU and RAM, then power consumption is significantly reduced, but the controller LSI loses the ability to issue release commands to peripheral devices

Engineering Contradiction:

Improvepower consumptionVSAvoiddevice control capability

Core Design Contradiction:

Use of energy by stationary objectVSEase of operation

Solution Approach 1:

Before the controller LSI enters deep power down mode, the control unit checks whether any peripheral devices are in deep power down mode. If so, it issues release commands in advance to ensure devices can be properly released when the controller resumes operation, maintaining control capability despite memory volatilization.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system preemptively counteracts the harmful effect of data volatilization by issuing release commands before entering low power consumption mode. This preliminary anti-action ensures that the loss of volatile memory data does not prevent proper peripheral device operation after the controller resumes.

Inventive Principle:

Principle #9Preliminary anti-action

3Adaptability or versatility

If the controller LSI stores state information in volatile memory to manage peripheral device modes, then device control is maintained, but transitioning to low power mode causes data loss and operational deadlock

Engineering Contradiction:

Improvedevice state managementVSAvoidoperational continuity

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The critical function of checking peripheral device operation modes and issuing release commands is extracted from the volatile memory-dependent control logic and implemented as a mandatory pre-power-down procedure. This ensures that essential device state management functions are preserved even when volatile memory data is lost during low power mode transitions.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS9575545B2LSI and information processing system

Publication Date: 2017.02.21 RENESAS ELECTRONICS CORP

AI summary

The controller LSI is connected to an SPI flash memory having a deep power down mode (DPM), and brings the SPI flash memory to the DPM and then brings itself to low power consumption mode (LPM) that volatilizes data in a RAM. This invention solves the problem that the controller LSI cannot release the peripheral device from the DPM upon returning from the LPM due to the volatilization of the data. The controller LSI includes a CPU, the RAM, and an SPI control unit transmitting an SPI command to the flash memory. The SPI command includes a power down command to bring the flash memory into DPM and a release command to release it from the DPM. Upon returning from the LPM, the controller LSI causes the control unit to transmit a release command to the flash memory irrespective of whether it is in DPM or normal mode.