Semiconductor Interconnect Embedding LSI and TSV in SoIS
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high integration density, miniaturization, and efficient communication bandwidth between semiconductor dies due to limitations in packaging techniques and interconnect structures, particularly in reducing silicon current leakage and avoiding pitting issues in molding processes.
Innovation Solution
The development of a high-routing-density interconnect device with fine-pitch die-to-die connections using a redistribution layer structure, including a polymer layer, conductive layers, and through molding vias, which are encapsulated and connected via external connectors to enhance communication bandwidth and reduce silicon current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional packaging techniques are used, then manufacturing simplicity is maintained, but integration density and communication bandwidth are limited
Solution Approach 1:
The interconnect device is divided into multiple functional layers including a substrate, conductive layers, dielectric layers, and molding compounds. Each layer performs a specific function, allowing the complex interconnect structure to be manufactured using standard semiconductor fabrication processes while achieving high integration density through systematic layering
Solution Approach 2:
The patent transitions from planar interconnect structures to three-dimensional stacked configurations with multiple conductive layers at different heights. This vertical dimensionality enables higher integration density by utilizing the Z-axis for additional interconnect paths while maintaining compatibility with conventional manufacturing techniques
2Productivity
If fine-pitch die-to-die connections are implemented, then communication bandwidth is improved, but silicon current leakage increases
Solution Approach 1:
A non-conductive molding compound is introduced as an intermediary material between adjacent conductive paths and die structures. This molding compound acts as an electrical insulator that prevents current leakage while allowing the fine-pitch interconnect structure to maintain high communication bandwidth through reduced signal path lengths
Solution Approach 2:
Different dielectric and molding materials with specific electrical properties are selectively applied in different regions of the interconnect device. The molding compound is specifically positioned around conductive vias and interconnect structures where current leakage is most problematic, providing localized electrical isolation without affecting the overall fine-pitch connection performance
3Reliability
If molding processes are used for encapsulation, then device protection is achieved, but pitting issues occur
Solution Approach 1:
The interconnect device is fully assembled with all conductive layers, vias, and die structures in place before the molding encapsulation process. This preliminary assembly ensures that the molding compound fills all gaps uniformly without creating voids or pits, as the structure is already complete and rigid enough to prevent material displacement during molding
Solution Approach 2:
The patent uses a composite structure combining multiple materials with different properties: conductive metals for interconnects, dielectric materials for insulation, and a non-conductive molding compound for encapsulation. This material combination provides both the mechanical protection needed for device reliability and the surface quality required to avoid pitting, as each material is selected for its specific functional properties
Data Source
AI summary
Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.