LSIFF Data Retention Flip-Flop for Low-Leakage Clock Isolation
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Solution Overview
Problem
Traditional data retention circuits in active power saving modes face challenges in timely status information restoration due to complexity in processing and distributing retention signals, leading to clock latency and increased power consumption through leakage current.
Innovation Solution
The implementation of a level shifting isolation flip flop (LSIFF) and a clock-controlled retention scheme (CCRS) that operate independently of retention signals, using a master slave flip flop with an output level shifter for data retention and providing output isolation, and a clock inverter to manage power domains, reducing power consumption and leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional data retention circuits are used in active power saving mode, then status information can be retained, but clock latency occurs due to complexity in processing and distributing retention signals
Solution Approach 1:
The patent extracts the retention signal processing logic from the critical data path by using a separate always-on power domain for the shadow latch. The RET signal is processed outside the main clock domain, eliminating clock latency in the data retention path while maintaining reliable status information storage across power domain boundaries.
Solution Approach 2:
The shadow latch acts as an intermediary between the master latch and the output, buffering status information independently of the RET signal processing. This mediator allows the main logic to operate without waiting for retention signal distribution, eliminating clock latency while preserving data integrity.
2Reliability
If traditional data retention flip flops and output isolation circuits are deployed, then data retention and voltage level matching are achieved, but power consumption increases due to leakage current
Solution Approach 1:
The patent segments the circuit into two power domains: a main power domain that can be powered down and an always-on power domain that supplies minimal power to the shadow latch and isolation circuitry. This segmentation allows the majority of the circuit to enter low-power mode while retaining essential data retention and isolation functionality, significantly reducing leakage current.
Solution Approach 2:
The always-on power domain is localized only to the shadow latch and isolation circuits that require continuous operation for data retention and voltage level matching. The rest of the circuit operates in the main power domain with dynamic power management, creating local quality differences in power supply that minimize overall power consumption while maintaining necessary functions.
Data Source
AI summary
An apparatus for providing active mode power reduction for circuits having data retention includes a master slave flip flop (MSFF) for latching a data input. An output level shifter (OLS), coupled to the MSFF, retains the data input in response to the MSFF being operable in an active power saving mode (APSM) to reduce power. The OLS operating in the APSM provides a level shifter output having a configurable voltage, thereby providing output isolation. A change in an operating mode of the MSFF between an active mode and the APSM is independent of a retention (RET) mode input.