Load-Store Unit Transaction Merging for Buffer Optimization
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Solution Overview
Problem
In processors with multiple cores, efficiently reconverting multiple transactions related to a single thread into a single transaction is challenging, especially when using bus protocols that support interleaving, leading to inefficient buffer storage and power usage.
Innovation Solution
A method where a load-store unit (LSU) converts a first transaction into multiple transactions, transfers them to a subordinate or cache with interleaving deactivation information, merges the data units, and reactivates interleaving when complete, using a single internal data buffer to optimize area and power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple transactions are converted from a single transaction for optimization, then processing speed is improved, but buffer storage efficiency deteriorates
Solution Approach 1:
The patent applies dynamics by making the buffer allocation adaptive rather than static. The system dynamically determines buffer allocation based on thread ID and transaction characteristics, switching between per-thread buffer allocation and unified buffer allocation depending on the specific processing scenario, thereby optimizing storage efficiency while maintaining high processing speed
Solution Approach 2:
The patent implements universality by designing a unified buffer that can serve multiple threads and transaction types. The buffer is configured to handle transactions from different threads through a single allocation, making the buffer structure multi-functional and reducing overall storage requirements while maintaining the ability to process multiple transactions efficiently
2Ease of operation
If separate buffers are provided for each thread, then transaction processing is simplified, but area and power consumption increase
Solution Approach 1:
The patent applies merging by combining multiple per-thread buffers into a single unified buffer structure. Instead of allocating separate buffers for each thread, the system merges all thread-related buffer needs into one shared buffer, significantly reducing the total buffer area while maintaining the ability to process transactions for multiple threads in an organized manner
Solution Approach 2:
The unified buffer is designed with multi-functionality to handle transactions from different threads. The buffer structure includes mechanisms to identify and manage transactions belonging to different threads within a single allocation, making the buffer both space-efficient and operationally viable for multi-threaded processing
3Ease of operation
If per-thread buffers are used, then data management is simplified, but power consumption increases
Solution Approach 1:
The patent merges multiple per-thread buffer structures into a single unified buffer, reducing the total number of buffer allocations and accesses. This consolidation decreases the overall power consumption of the buffer system while maintaining effective data management through thread-aware booking and allocation mechanisms within the unified structure
Data Source
AI summary
A method for processing multiple transactions converted from a single transaction related to each of a plurality of threads is provided, in which the method is performed by a processor including at least one core and includes converting a first transaction related to at least one of the plurality of threads into a plurality of second transactions, transferring, by a load-store unit (LSU) of the core, the plurality of second transactions to a subordinate or a cache, receiving, by the LSU, a plurality of data units related to the second transactions from the subordinate or the cache, and merging, by the LSU, the plurality of data units, in which the LSU is configured to further transfer interleaving deactivation information that causes the subordinate or the cache to deactivate interleaving.