Large Touch Display Integrated Circuit Boot Verification
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Solution Overview
Problem
Existing SPI architectures face inefficiencies in booting up multiple slave ICs due to the need for individual handshake mechanisms, leading to prolonged boot times in large touch display integrated circuit applications.
Innovation Solution
Implementing a reload circuit and open-drain circuit in slave ICs to broadcast an open-drain signal via a correctness wire, allowing the master IC to determine the correctness of boot up codes across multiple slave ICs simultaneously, eliminating the need for individual CRC code readbacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the master IC transmits boot up code to multiple slave ICs using traditional SPI handshake mechanism one at a time, then each slave IC can be confirmed to receive the correct code, but the boot time becomes prolonged and inefficient
Solution Approach 1:
The patent merges multiple individual CRC check operations into a single collective check by connecting all slave ICs' CRC outputs through open-drain circuits to a common wire. This allows the master IC to verify all slave ICs simultaneously rather than sequentially, resolving the contradiction between reliable verification and time efficiency.
Solution Approach 2:
The patent uses open-drain circuit copying where each slave IC's CRC result is copied to the common correctness wire through its open-drain output. This enables parallel verification of multiple slaves without requiring the master to individually query each one, significantly reducing boot time while maintaining verification reliability.
2Reliability
If individual handshake mechanisms are used for each slave IC, then code correctness can be verified, but the device complexity and operation complexity increase
Solution Approach 1:
The patent combines multiple individual handshake operations into a single collective verification process. By using open-drain circuits to merge all CRC outputs onto one correctness wire, the system reduces operational complexity while maintaining the reliability of code verification across all slave ICs.
Solution Approach 2:
Each slave IC autonomously calculates its CRC and automatically outputs the result to the common correctness wire through its open-drain circuit without requiring individual master intervention. This self-service mechanism simplifies the overall system operation while ensuring reliable verification of each slave's code integrity.
3Reliability
If individual CRC readbacks are required for each slave IC, then code correctness can be confirmed, but the boot process becomes slower and less efficient
Solution Approach 1:
The patent enables continuous parallel verification by having all slave ICs continuously monitor the correctness wire and immediately signal their CRC status. This eliminates the sequential stop-start nature of individual readbacks, maintaining continuous useful action during the boot process and significantly improving boot efficiency while preserving verification reliability.
Solution Approach 2:
Each slave IC preliminarily calculates and prepares its CRC result in advance, holding it ready in its output circuit before the master needs to verify. This preliminary preparation allows the master to verify all slaves simultaneously without waiting for individual computation, thereby improving boot efficiency while ensuring reliable verification.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient and simplified booting of multiple slave ICs by allowing the master IC to determine code correctness collectively, reducing boot time and enhancing operational efficiency.
Implementation Method 1
the slave ICs with an error may pull down the potential of the correctness wire to a low logic level
Implementation Method 2
when the boot up code received by these slave ICs are all correct, these slave ICs are all in a high-impedance state (Hi-Z) for the correctness wire, and at this time, the first pull-up resistor may pull up the potential of the correctness wire to a high logic level
Data Source
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AI summary
The invention provides a large touch display integrated (LTDI) circuit (S21, S2n, 320, 620) and an operation method thereof. The LTDI circuit (S21, S2n, 320, 620) is suitable as a slave IC of an serial peripheral interface (SPI) architecture (200, 500). The LTDI circuit (S21, S2n, 320, 620) includes an open-drain circuit (322, 622) and a reload circuit (321, 621). An output terminal of the open-drain circuit (322, 622) is configured to be coupled to a correctness wire (CW) outside the LTDI circuit (S21, S2n, 320, 620). The correctness wire (CW) is coupled to an input terminal of a master IC (M21) of the SPI architecture (200, 500), and a potential of the correctness wire (CW) is pulled up by a pull-up resistor (312, 612). The reload circuit (321, 621) is coupled to an input terminal of the open-drain circuit (322, 622). The reload circuit (321, 621) is configured to check a correctness of a boot up code from the master IC (M21) to generate a correctness check result. The reload circuit (321, 621) returns the correctness check result to the master IC (M21) via the open-drain circuit (322, 622) and the correctness wire (CW).