LTPO Array Base Plate Capacitor Vertical Stacking
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Solution Overview
Problem
In the field of display technology, particularly with LTPO technology, it is challenging to increase the storage capacitance area of the array base plate without compromising the resolution and introducing signal crosstalk.
Innovation Solution
The array base plate design relocates the capacitor, allowing the electrode plate to be extended or offset, thereby increasing the capacitance area. This design also positions the second electrode plate above the transistors, reducing signal crosstalk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the capacitor structure is located between LTPS device and IGZO device in conventional LTPO array base plate, then the device integration is achieved, but the area of electrode plate of storage capacitor cannot be increased which limits resolution improvement
Solution Approach 1:
The capacitor structure is relocated from the planar configuration between LTPS and IGZO devices to a vertical stacked configuration. The first electrode plate is positioned on the same layer as source-drain electrodes while the second electrode plate is positioned above the transistor, utilizing the thickness direction (Z-axis) to create capacitance area without consuming additional planar area. This dimensional transition enables resolution improvement by effectively increasing the electrode plate area in three-dimensional space.
2Device complexity
If the capacitor is positioned in the conventional location, then the device layout is simplified, but signal crosstalk risk increases
Solution Approach 1:
The second electrode plate of the capacitor is positioned in the thickness direction above the transistor structure, separating it vertically from signal transmission lines in the planar layer. This spatial separation in the Z-dimension reduces electromagnetic coupling and signal crosstalk between the capacitor and surrounding circuits, while the capacitor remains integrated into the device layer structure.
3Manufacturing precision
If the electrode plate area is increased to improve resolution, then the capacitance area increases, but the available planar space on the array base plate is reduced
Solution Approach 1:
The capacitor electrode plates are arranged in a stacked configuration where the first electrode plate lies in the planar layer and the second electrode plate extends in the thickness direction. This vertical arrangement allows the electrode plate area to be increased without occupying additional planar space, as the capacitance area is developed along the Z-axis rather than consuming XY-plane area.
Solution Approach 2:
The capacitor structure is nested within the existing transistor structure by positioning the second electrode plate above the transistor in the thickness direction. This nesting approach allows the capacitor to share the vertical space above the active device area, increasing capacitance area without encroaching on the planar space required for other display elements.
Data Source
AI summary
The present application relates to an array base plate, a display panel, and a method for manufacturing an array base plate, and the array base plate includes: a substrate; a device layer stacked on a side of the substrate along a thickness direction thereof, wherein the device layer includes a first type transistor, a second type transistor, and a capacitor, the first type transistor includes a first source-drain electrode, the second type transistor includes a second source-drain electrode, and the capacitor includes a first electrode plate and a second electrode plate; wherein the first electrode plate is provided on the same layer as at least one of the first source-drain electrode and the second source-drain electrode, and the second electrode plate is provided on a side of the first type transistor and the second type transistor away from the substrate along the thickness direction.