Miniaturized LTE Antenna Structure for Bandwidth and Efficiency
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Solution Overview
Problem
Existing small form factor LTE antennas face challenges in minimizing size while maintaining efficiency due to inherent capacitance and parasitic capacitances, which degrade bandwidth capabilities and result in efficiency dropouts within the intended operating bandwidth.
Innovation Solution
The design incorporates a dielectric substrate with specific metallization layers and through hole vias that connect discrete metallizations in a way that minimizes overlap and maximizes radiation efficiency, including features like choke points, truncation, and staircasing, to reduce capacitance and enhance bandwidth, allowing for a smaller form factor of 27mm by 10mm by 1.6mm, a 292% reduction in volume compared to prior antennas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the antenna form factor is minimized to reduce device size, then the volume is reduced, but inherent capacitance and parasitic capacitances increase, degrading bandwidth capabilities and causing efficiency dropouts
Solution Approach 1:
The antenna is divided into multiple discrete metallization elements (first through ninth discrete metallizations) arranged in specific patterns on dielectric substrates. These segmented elements are connected through controlled via structures, allowing independent optimization of each segment to reduce overall capacitance while maintaining resonant frequencies. The segmentation enables the antenna to achieve miniaturization without the capacitance penalties of monolithic small antennas.
Solution Approach 2:
Different regions of the antenna structure are designed with locally optimized properties. The discrete metallizations have varying shapes, sizes, and positions (including L-shaped, U-shaped, and rectangular configurations) to create localized resonant structures. The dielectric substrates have specific permittivity values assigned to different layers, and via structures are strategically placed with controlled dimensions to manage capacitance distribution throughout the antenna volume.
2Volume of moving object
If the antenna form factor is minimized, then the volume is reduced, but parasitic capacitances are generated, resulting in efficiency dropouts within the operating bandwidth
Solution Approach 1:
Parasitic capacitance elements are explicitly identified and extracted from the antenna structure through careful design. The via structures are designed with specific dimensions and spacing to minimize unwanted capacitance, and discrete metallizations are positioned to avoid creating parasitic resonant modes. Ground plane configurations are optimized to extract and manage parasitic effects, isolating them from the main radiating elements.
Solution Approach 2:
The design converts potentially harmful parasitic capacitances into useful features. Certain via structures and metallization configurations are designed to create controlled capacitance values that actually enhance bandwidth or create additional resonant modes. The discrete metallization patterns are arranged to transform what would be parasitic elements into complementary radiating structures that broaden the operating bandwidth.
Data Source
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AI summary
A miniaturized long-term evolution (LTE) antenna (100). In one embodiment, the antenna (100) includes a dielectric substrate comprising a first surface and a second opposing surface; a first metallization layer (200) disposed on the first surface of the dielectric substrate, the first metallization layer comprising a first metallization (210), a second metallization (220), a third metallization (230), and a fourth metallization (240); and a second metallization layer disposed on the second opposing surface of the dielectric substrate, the second metallization layer (250) comprising a fifth metallization (260), a sixth metallization (270), a seventh metallization (280), an eighth metallization (290), and a ninth metallization (295). The antenna includes a plurality of through hole vias (202) that: connect the first metallization (210) with the fifth metallization (260); connect the second metallization (220) with both the sixth metallization (270) and the seventh metallization (280); and connect the fourth metallization (240) with both the fifth metallization (260) and the sixth metallization (270). System level implementations are also disclosed.