LTE Rate Matching Using Reused Padding Bit Positions
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Solution Overview
Problem
Existing rate matching techniques in LTE systems introduce latency and require significant memory usage, which need to be minimized for efficient data transmission.
Innovation Solution
A method and device for rate matching that determines and stores padding bit positions at the beginning of a transmission time interval, allowing for efficient buffering and pruning of output bits from the channel encoding stage to match the physical transmission channel's data rate, with the option to reuse these positions for each code block, and performs bit position determination in parallel to channel encoding to minimize latency and memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional rate matching operations are performed with full buffering and sequential processing, then the rate matching can be completed accurately according to LTE specifications, but the latency in the data transmission process increases and memory usage increases
Solution Approach 1:
The patent pre-calculates and stores the positions of padding bits (dummy bits and filler bits) in the output buffer before the actual rate matching operation. This preliminary determination of bit positions allows the channel encoder output to be directly placed in correct positions without sequential searching or buffering, thereby reducing latency while maintaining accurate rate matching according to LTE specifications.
2Reliability
If conventional rate matching with full output buffering is implemented, then all channel encoder outputs can be stored and processed, but the memory usage required for the rate matching increases
Solution Approach 1:
The patent extracts and stores only the essential information needed for rate matching - specifically the positions of padding bits - rather than buffering the entire channel encoder output. By removing the need to store all intermediate bits and keeping only the critical position information, memory usage is significantly reduced while the rate matching operation remains complete and accurate.
3Reliability
If sequential processing of channel encoder outputs is used, then the rate matching can be performed correctly, but the processing time and latency increase
Solution Approach 1:
The patent performs preliminary calculation of padding bit positions independently of the channel encoding process. This pre-computed position information is then used during rate matching to directly place channel encoder outputs in their correct positions without sequential processing delays, thereby increasing processing speed while maintaining accuracy.
Solution Approach 2:
The patent enables continuous parallel operation of channel encoding and position determination processes. By having the position information ready in advance and using direct placement rather than sequential processing, the useful action of data transmission continues without interruption or delay, improving overall processing speed and productivity.
Data Source
AI summary
A technique for rate matching a bit stream (c(0-2)(k)) output from a channel encoder (102) to a data transmission rate on a physical transmission channel is described. A method embodiment of the technique comprises the steps of determining, at a beginning of a transmission time interval for a transmission of one or more code blocks on the transmission channel, bit positions of interleaver padding bits (dummy and/or filler bits) in an output buffer for buffering the output bits before transmission on the physical transmission channel; storing the determined padding bit positions (114); and determining, based on the stored padding bit positions, positions (d(0-2)(k)) of the output bits from the channel encoding stage (102) in the output buffer, wherein the stored padding bit positions are re-used for each of the one or more code blocks.