LTE Turbo Decoder Memory Architecture With Single-Bank Parallel Access
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Solution Overview
Problem
Conventional multi-processing architectures for LTE turbo decoders require a multibank memory with parallel access to achieve high bit-rates, leading to increased complexity and die area, especially as parallelism grows, necessitating a more efficient memory access solution.
Innovation Solution
Implementing a single-bank memory architecture with a decoder circuit that generates a single address signal for reading and writing systematic and a-priori-information signals during alternating half-iterations, utilizing a QPP-interleaver to enable parallelism without memory contentions, and using a single AGU for vector data access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a multibank memory with parallel access is used to achieve high bit-rates in LTE turbo decoders, then the decoding speed and bit-rate are improved, but the device complexity and die area increase significantly
Solution Approach 1:
The patent segments the decoding process into two distinct phases: odd half-iterations and even half-iterations. During odd half-iterations, the decoder reads systematic information data and first a-priori-information; during even half-iterations, it reads second parity data and second a-priori-information. This temporal segmentation allows a single memory bank to serve multiple functions that would otherwise require parallel multibank access, thereby reducing memory architecture complexity while maintaining decoding speed.
Solution Approach 2:
The patent implements dynamic memory access patterns where the same memory bank is accessed differently depending on the iteration phase. The memory bank dynamically switches between providing systematic information data during odd iterations and providing parity data during even iterations. This dynamic utilization allows one memory bank to replace multiple static banks, reducing overall device complexity and die area.
2Productivity
If the parallelism degree is increased to achieve higher bit-rates, then the decoding performance is improved, but the number of address generation units (AGUs) and memory banks must increase linearly, increasing die area
Solution Approach 1:
The patent employs periodic action by alternating between two distinct access modes: odd half-iterations for reading systematic information and first a-priori-information, and even half-iterations for reading second parity data and second a-priori-information. This periodic switching allows a single memory bank to handle data access for multiple parallel processing units over time, achieving high bit-rates without requiring a proportional increase in memory bank count or die area.
Solution Approach 2:
The patent merges the functions of multiple memory banks into a single memory bank by combining different data access operations in time. The single memory bank simultaneously serves as the source for systematic information data during odd iterations and for parity data during even iterations, effectively consolidating what would traditionally require separate dedicated memory banks for each data type and processing unit.
3Area of stationary object
If a single bank of memory is used instead of multibank memory, then the die area is reduced, but memory access contentions may occur that could stall processing
Solution Approach 1:
The patent resolves potential memory access contentions through dynamic phase-based access control. By dividing the decoding process into odd and even half-iterations with distinct memory access patterns, the system ensures that only one type of data access occurs at any given time. This dynamic temporal separation eliminates simultaneous access conflicts that would otherwise stall processing, maintaining reliability while using a single memory bank.
Solution Approach 2:
The patent maintains continuous processing by ensuring that the single memory bank is continuously utilized without stalls. During odd half-iterations, the bank provides systematic information and a-priori-information; during even half-iterations, it provides parity data. This continuous alternating access pattern ensures no processing idle time occurs, maintaining the reliability and throughput equivalent to multibank systems while reducing die area.
Data Source
AI summary
An apparatus comprising a decoder circuit and a memory. The decoder circuit may be configured to generate a single address signal to read a first parity data signal, a second parity data signal and read and/or write systematic information data, a first a-priori-information signal and a second a-priori-information signal. The decoder circuit (i) reads the first parity data signal, the systematic information data and the first a-priori-information during even half-iterations of a decoding operation and (ii) reads the second parity data, the systematic information data and the second a-priori-information during odd half-iterations of the decoding operation. The memory may be configured to store the systematic information data and the first and second a-priori-information signals such that each are accessible by the single address signal.