LTPO Shift Register Noise Reduction Circuit

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Solution Overview

Problem

Low temperature polycrystalline oxide (LTPO) pixel driving circuits face challenges in achieving high charge mobility and stability while maintaining low production costs, particularly due to the low charge mobility of N-type oxide TFTs used for scanning and reset transistors.

Innovation Solution

A shift register design incorporating a specific configuration of input, control, noise reduction, and output sub-circuits, utilizing thin film transistors and capacitors to enhance voltage control and signal transmission, thereby improving the output ability of the gate driver circuit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If N-type oxide TFTs are used for scanning and reset transistors to achieve low production costs and high stability, then manufacturing cost and stability are improved, but charge mobility deteriorates

Engineering Contradiction:
Improveproduction costVSAvoidcharge mobility
Core Design Contradiction:
Ease of manufactureVSSpeed

Solution Approach 1:

The shift register is divided into multiple sub-circuits (first input sub-circuit, second input sub-circuit, first control sub-circuit, second control sub-circuit, noise reduction sub-circuit, and output sub-circuit) that work together to compensate for the low charge mobility of N-type oxide TFTs while maintaining cost-effectiveness

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces multiple clock signals (first clock signal, second clock signal, third clock signal) and voltage signals to dynamically control the timing and sequence of operations in different sub-circuits, optimizing the performance of N-type oxide TFTs by adjusting operational parameters rather than changing the fundamental device type

Inventive Principle:
Principle #35Parameter changes

2Reliability

If multiple sub-circuits are added to improve output ability and reduce noise, then signal stability and noise reduction are improved, but device complexity increases

Engineering Contradiction:
Improvesignal stabilityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The shift register is divided into multiple sub-circuits (first input sub-circuit, second input sub-circuit, first control sub-circuit, second control sub-circuit, noise reduction sub-circuit, and output sub-circuit) that work together to compensate for the low charge mobility of N-type oxide TFTs while maintaining cost-effectiveness

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple functional sub-circuits are integrated into a unified shift register structure that processes both clock signals and voltage signals through coordinated operations, achieving noise reduction and signal stabilization while sharing common control mechanisms

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12125546B2Shift register and driving method therefor, gate driver circuit, and display apparatus
Publication Date: 2024.10.22 CHENGDU BOE OPTOELECTRONICS TECH CO LTD
  • US12125546B2 patent drawing
  • US12125546B2 patent drawing
  • US12125546B2 patent drawing

AI summary

A shift register includes a first input sub-circuit being configured to transmit an input signal to a first node under control of a first clock signal; a second input sub-circuit being configured to transmit a first voltage signal to a second node under control of the first clock signal; a first control sub-circuit being configured to transmit a second clock signal to a third node under control of a voltage at the second node; a second control sub-circuit being configured to transmit the first voltage signal to a fourth node under control of a third clock signal; a noise reduction sub-circuit being configured to transmit the first voltage signal to a signal output terminal under control of a voltage at the fourth node; and an output sub-circuit being configured to transmit a second voltage signal to the signal output terminal under control of a voltage at the third node.