LTPO Array Substrate Gate Line Configuration for Pull-Down Compensation
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Solution Overview
Problem
In pixel driving circuits formed using low temperature polycrystalline oxide (LTPO) technology, the N-type metal oxide transistor's gate electrode pull-down effect on the driving transistor's gate electrode affects charging, requiring higher voltage data signals for normal display, which existing source driving circuits cannot meet.
Innovation Solution
The array substrate design includes a pixel driving circuit with P-type driving and N-type transistors, where the gate line configuration and conductive layer arrangements reduce lateral capacitance between transistors, enhancing the pull-up effect on the driving transistor's gate electrode, thereby offsetting the pull-down effect and ensuring adequate voltage for proper operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the N-type metal oxide transistor is used in the pixel driving circuit, then the transistor can provide good switching performance, but it causes a pull-down effect on the gate electrode of the driving transistor which affects charging
Solution Approach 1:
A first capacitor is introduced as an intermediary component between the N-type metal oxide transistor and the gate electrode of the driving transistor. The capacitor couples the gate signal to the gate electrode, allowing the N-type transistor to maintain its switching performance while the capacitor blocks the direct pull-down effect on the gate electrode, thus resolving the contradiction between switching performance and harmful pull-down effect.
2Reliability
If the gate line is positioned close to the first conductive portion, then the lateral capacitance is increased to enhance pull-up effect, but the area occupied by the gate line increases
Solution Approach 1:
The gate line is configured to extend in a first direction parallel to the second direction where the first conductive portion extends, rather than perpendicular to it. This dimensional reorientation allows the gate line to achieve sufficient lateral capacitance coupling with the first conductive portion while occupying less area in the plane, effectively resolving the contradiction between enhancing pull-up effect and minimizing gate line area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design ensures the driving transistor outputs the required current by reducing the pull-down effect of the N-type transistor on the driving transistor's gate electrode, allowing for normal display performance even at lower voltage data signals, such as 6V, and reduces power consumption by minimizing differences in driving voltages across different pixel units.
Implementation Method 1
a first conductive layer arranged at a side of the base substrate and including a first conductive portion, a first gate line and a second gate line. The first conductive portion is configured to form a gate electrode of the driving transistor. The first gate line is located at a side of the first conductive portion
Implementation Method 2
An orthographic projection of the first extending portion on the base substrate is opposite to an orthographic projection of at least a part of the first conductive portion on the base substrate in the first direction
Data Source
AI summary
This disclosure provides an array substrate and a display device. In the array substrate, the pixel driving circuit includes a driving transistor, a first transistor and a second transistor. The driving transistor and the first transistor are P-type transistors, and the second transistor is N-type transistor. The array substrate also includes a base substrate, and a first conductive layer arranged at a side of the base substrate and including: a first conductive portion forming a gate electrode of the driving transistor; a first gate line at a side of the first conductive portion, a part of the first gate line being configured to form a gate electrode of the first transistor; and a second gate line at a side of the first gate line away from the first conductive portion, a part of the second gate line being configured to form a first gate electrode of the second transistor.