LTPO Transistor Stack Barrier Layer Against Hydrogen Diffusion

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Solution Overview

Problem

In current low temperature polycrystalline oxide (LTPO) technology, excessive hydrogen ions diffuse into metal oxide semiconductor elements, affecting their characteristics and performance.

Innovation Solution

Incorporating a barrier layer between the first and second semiconductor layers to block hydrogen ion diffusion, and optimizing the layout of transistors and organic layers to enhance performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If metal oxide semiconductor elements are formed in current LTPO technology processes, then the device structure is completed, but excessive hydrogen ions diffuse into the metal oxide semiconductor elements, affecting their characteristics

Engineering Contradiction:
Improveperformance of metal oxide semiconductor elementsVSAvoidhydrogen ion diffusion
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A barrier layer is introduced as an intermediary component between the metal oxide semiconductor layer and the surrounding environment. This barrier layer specifically blocks hydrogen ion diffusion while allowing the metal oxide semiconductor elements to function normally, thus protecting the semiconductor elements from hydrogen ion contamination without affecting their operational characteristics.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The barrier layer is positioned in advance to prevent hydrogen ion diffusion before the hydrogen ions can reach and damage the metal oxide semiconductor elements. By establishing this protective barrier during the manufacturing process, the harmful effects of hydrogen ion diffusion are preemptively blocked, preserving the semiconductor element characteristics.

Inventive Principle:
Principle #9Preliminary anti-action

2Reliability

If a barrier layer is added to block hydrogen ion diffusion, then the performance of metal oxide semiconductor elements is improved, but the device structure becomes more complex

Engineering Contradiction:
Improveperformance of metal oxide semiconductor elementsVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The barrier layer is applied selectively only in regions where hydrogen ion diffusion is a problem, specifically around the metal oxide semiconductor elements. This localized approach provides targeted protection where needed while avoiding unnecessary complexity in other parts of the device structure, thus improving semiconductor performance without proportionally increasing overall device complexity.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The barrier layer effectively reduces hydrogen ion diffusion, maintaining the performance of metal oxide semiconductor elements and improving the overall functionality of the electronic device.

Implementation Method 1

a barrier layer disposed between the first semiconductor layer and the second semiconductor layer. In current low temperature polycrystalline oxide (LTPO) technology, excessive hydrogen ions may diffuse into the metal oxide semiconductor elements, thereby affecting the characteristics of the metal oxide semiconductor elements

Methodology Applied
Scientific EffectDiffusion barrier: Diffusion Barrier

Data Source

PatentUS12588289B2Electronic device
Publication Date: 2026.03.24 INNOLUX CORP
  • US12588289B2 patent drawing
  • US12588289B2 patent drawing
  • US12588289B2 patent drawing

AI summary

An electronic device is provided by the present disclosure. The electronic device includes a substrate; a first transistor disposed on the substrate and including a first semiconductor layer and a gate electrode; a first insulating layer disposed between the first semiconductor layer and the gate electrode; a second insulating layer disposed on the first insulating layer, wherein the first semiconductor layer and the gate electrode are located between the substrate and the second insulating layer; a barrier layer disposed on the second insulating layer; and a second transistor disposed on the barrier layer and including a second semiconductor layer, wherein the barrier layer is disposed between the second semiconductor layer and the second insulating layer.