LTPO Display Substrate Gate Layout for Narrow Bezel Panels
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Solution Overview
Problem
The introduction of Gate N GOA circuits in LTPO display panels increases the width of the border area, hindering the development of narrow bezel designs.
Innovation Solution
The design incorporates a nested arrangement of gate driving circuits with partially overlapping boundary areas, eliminating gaps between adjacent circuits and utilizing a planarization layer to cover all gate driving circuits, allowing for space mixture and reduced border width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If Gate N GOA circuits are introduced to reduce power consumption, then power consumption is reduced, but the border area width increases
Solution Approach 1:
The patent applies nesting by arranging the first gate driving circuit, second gate driving circuit, and third gate driving circuit in an overlapping nested configuration where their orthographic projections partially coincide. This nested arrangement allows the circuits to share space vertically through multiple layers, significantly reducing the horizontal border area width while maintaining all necessary circuit functions for power consumption reduction.
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked configuration by placing gate driving circuits in multiple layers (first, second, and third gate driving circuits at different vertical levels). This dimensional change enables the circuits to occupy overlapping horizontal projections without physical interference, reducing the border width while preserving all circuit functionalities.
2Length of stationary object
If gate driving circuits are arranged with overlapping projections to reduce border width, then border area width is reduced, but circuit layout complexity increases
Solution Approach 1:
The patent segments the gate driving circuits into three distinct functional groups (first gate driving circuit connected to P-type transistors, second gate driving circuit connected to N-type transistors, third gate driving circuit for additional control). This segmentation allows each circuit group to be independently designed and optimized, simplifying the overall layout process despite the nested three-dimensional arrangement.
Data Source
AI summary
A display substrate includes: a base substrate; light-emitting elements located in a display area; pixel driving circuits located respectively connected to the light-emitting elements, each pixel driving circuit including an N-type transistor and a P-type transistor; a first gate driving circuit, a second gate driving circuit and a third gate driving circuit in a border area of the display area, the first and third gate driving circuits being connected with the P-type transistor, the second gate driving circuit being connected with the N-type transistor, and orthographic projections of the first to third gate driving circuits on the base substrate are not overlapped with each other; and a planarization layer located between the pixel driving circuits and the light-emitting elements.