LTPS Array Substrate Layout for Flicker-Stable Pixel Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Liquid crystal display panels using low-temperature polysilicon (LTPS) suffer from light-induced leakage current, causing pixel voltage fluctuations and abnormal flicker due to the incomplete light-shielding effect of the light-shielding layer.
Innovation Solution
An array substrate design featuring a light-shielding layer with multiple light-shielding portions and transistors arranged such that orthographic projections of source and drain terminals are strategically located on these portions, allowing voltage jumps to compensate for leakage current-induced voltage drops, thereby enhancing pixel brightness and reducing flicker.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a light-shielding layer is added to reduce light-induced leakage current, then leakage current is reduced, but the light-shielding layer cannot completely eliminate the leakage current causing pixel voltage fluctuation and abnormal flicker
Solution Approach 1:
The light-shielding layer is segmented into multiple light-shielding portions disposed at intervals rather than a continuous layer. This segmentation allows the source terminal and drain terminal of adjacent transistors to be positioned on different light-shielding portions, enabling the parasitic capacitance effect to compensate for voltage drops and eliminate pixel voltage fluctuation and abnormal flicker while maintaining effective light shielding
Solution Approach 2:
The light-shielding portion acts as an intermediary element that simultaneously provides light shielding and enables parasitic capacitance coupling between adjacent transistors. The spaced arrangement of light-shielding portions creates capacitive coupling that compensates for voltage drops caused by leakage current, thereby stabilizing pixel voltage without requiring a continuous light-shielding layer
2Ease of manufacture
If source terminal and drain terminal of adjacent transistors are positioned on the same light-shielding portion, then manufacturing is simplified, but voltage fluctuation and abnormal flicker occur due to incomplete shielding
Solution Approach 1:
The light-shielding layer is divided into multiple spaced light-shielding portions, which is achieved through standard photolithography and etching processes. This segmentation enables the source terminal and drain terminal of adjacent transistors to be positioned on different light-shielding portions, creating parasitic capacitance coupling that compensates for voltage drops and eliminates abnormal flicker while maintaining ease of manufacture
Solution Approach 2:
Different regions of the light-shielding layer have different functions: the light-shielding portions provide optical shielding, while the spaced arrangements between portions enable parasitic capacitance coupling. This local differentiation of function allows the structure to simultaneously achieve light shielding and voltage stabilization without complicating the manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases the absolute voltage of the drain terminal of adjacent transistors, compensating for leakage current decreases and improving pixel brightness and stability, thus addressing the issue of abnormal flicker in display panels.
Implementation Method 1
a light-shielding layer disposed on the base substrate and comprising a plurality of light-shielding portions disposed at intervals
Implementation Method 2
coupled with parasitic capacitance to compensate for voltage drops
Data Source
AI summary
An array substrate comprises a base substrate, a light-shielding layer disposed on the base substrate, and a plurality of transistors disposed in an array on a side of the light-shielding layer away from the base substrate. The light-shielding layer comprises a plurality of light-shielding portions. Orthographic projections of a source terminal of each of the transistors and a drain terminal of one adjacent transistor in a same row on the base substrate are located on one same light-shielding portion, and orthographic projections of a source terminal and a drain terminal of one same transistor on the base substrate are respectively located on two adjacent light-shielding portions that are spaced apart. A display panel comprises the array substrate.