LTPS Array Substrate Mask Plate Reduction via Gate Electrode
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The manufacturing process of Low-temperature polysilicon (LTPS) thin film transistors is complex and costly due to the high frequency and number of mask plates used, particularly in forming via holes and doping ions, which increases the overall manufacturing cost.
Innovation Solution
A method is introduced where a mask pattern with a hollowed-out portion and two distinct thickness portions is formed, allowing the gate electrode to act as a light shield and reducing the need for additional light shielding layers, and using the mask pattern for ion implantation, thereby minimizing the use of mask plates and simplifying the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional patterning processes are used to form via holes and dope ions, then the manufacturing process follows conventional steps, but the number of mask plates increases and manufacturing cost increases
Solution Approach 1:
The patent combines the light shielding function and ion doping mask function into a single integrated structure. The gate electrode serves dual purposes: as the light shielding layer during active layer formation and as the mask pattern for subsequent ion implantation. This merging eliminates the need for separate mask plates in these critical steps, directly reducing mask plate quantity while maintaining manufacturing feasibility
Solution Approach 2:
The gate electrode is designed to perform multiple functions sequentially: first as a light shielding layer during active layer photolithography, then as a mask pattern for ion implantation. This multi-functionality allows one structure to replace what traditionally required multiple separate components (light shielding layer plus mask plates), resolving the contradiction between ease of manufacture and mask plate quantity
2Reliability
If a light shielding layer is formed separately, then the active layer is protected from light influence, but the manufacturing process complexity increases
Solution Approach 1:
The light shielding function is merged into the gate electrode structure itself. During active layer formation, the gate electrode naturally blocks light from reaching regions where the active layer should not be formed. This eliminates the need for a separate light shielding layer and its associated patterning steps, reducing manufacturing process complexity while maintaining active layer protection
Solution Approach 2:
The gate electrode serves its primary function as an electrical conductor while simultaneously providing light shielding protection during fabrication. This self-service capability means the gate electrode protects itself and the active layer without requiring additional dedicated structures, thereby reducing overall device complexity in the manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of mask plates required, lowers manufacturing costs, and simplifies the process by using the gate electrode for light shielding and the mask pattern for ion implantation, while maintaining the high electron mobility and reliability of LTPS thin film transistors.
Implementation Method 1
the gate electrode can be used as a mask during doping ions, but it is still necessary to additionally form a light shielding layer through a single patterning process, to prevent the active layer from being influenced by light
Implementation Method 2
forming a mask pattern, where the mask pattern includes a hollowed-out portion, a first portion and a second portion... the second portion has a thickness smaller than the first portion... implanting ions into the active layer
Data Source
AI summary
A method for manufacturing an array substrate includes (S1) forming a pattern including a gate electrode and a gate line, (S2) forming an insulating layer, (S3) forming a pattern including an active layer, where the region where the active layer is arranged includes a first region corresponding to the gate electrode and second regions arranged on both sides of the first region, (S4) forming a mask pattern including a hollowed-out portion, a first portion and a second portion, wherein the second portion has a thickness smaller than the first portion, (S5) etching the insulating layer to form a via hole for exposing a portion of the gate line, and (S6) ashing a portion of the mask pattern corresponding to the second region to remove the portion of the mask pattern corresponding to the second region, and implanting ions into the active layer.