LTPS Array Substrate Gate Masking for Fabrication Yield
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Solution Overview
Problem
Conventional methods for fabricating array substrates using low temperature poly-silicon (LTPS) are complex, costly, and have low product yield due to the need for multiple masks in the CMOS process.
Innovation Solution
A method involving a transparent substrate with a buffer layer, gate patterns, and polysilicon patterns, where the gate patterns act as light shielding layers to form photoresist patterns without additional masks, allowing for doping and source/drain formation with fewer mask steps, simplifying the process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CMOS fabrication method with multiple masks is used, then light shielding and channel protection can be achieved, but the process becomes complex and fabricating cost increases
Solution Approach 1:
The patent combines the light shielding layer and channel protection function into a single gate structure. The gate pattern serves dual purposes: as a light shielding layer during photolithography and as a protective structure for the channel, eliminating the need for separate shielding layers and reducing the number of masks required.
Solution Approach 2:
The gate structure is designed to perform multiple functions simultaneously: it acts as an electrical gate for transistor operation, a light shielding layer during fabrication, and a protective structure for the channel. This multi-functionality reduces process complexity while maintaining reliability.
2Manufacturing precision
If conventional CMOS fabrication method is used, then proper doping regions can be formed, but the number of masks increases to 11 and product yield decreases
Solution Approach 1:
The patent performs preliminary doping actions during the gate formation process itself. The gate pattern is used as a mask for preliminary doping of the source and drain regions, and subsequent self-aligned doping steps are performed without requiring additional masks, thereby maintaining precision while improving yield.
Solution Approach 2:
The gate structure serves as its own masking layer for doping operations. The gate pattern automatically defines the doping regions through self-alignment, eliminating the need for separate masking steps and reducing the total number of masks from 11 to fewer steps, thus improving product yield.
3Manufacturing precision
If top gate structures with additional shielding layers are used, then self-aligned LDD can be achieved, but contact resistance between source/drain and LDD increases
Solution Approach 1:
The patent removes the additional interlayer shielding structures that were previously necessary for self-aligned LDD formation. By taking out these extra layers, the source and drain electrodes can directly contact the lightly doped drain regions, reducing contact resistance while maintaining self-alignment through the gate pattern.
Solution Approach 2:
Instead of using additional shielding layers to achieve self-alignment (adding complexity), the patent inverts the approach by using the gate structure itself as the alignment reference. This eliminates the need for extra shielding layers and enables direct contact between source/drain and LDD, reducing contact resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method reduces the number of masks required, simplifies the fabrication process, lowers costs, and improves product yield by eliminating the need for additional shielding layers and directly contacting sources/drains with heavily doped regions, thereby reducing contact resistance.
Implementation Method 1
The first doping step is to dope a plurality of n-type dopants into the second region and the fourth region by using an ion implanting process
Data Source
AI summary
An array substrate and a fabricating method thereof are disclosed. The array substrate has a transparent substrate, a buffer layer, a first/second gate pattern, a transparent insulating layer and a first/second polysilicon pattern. The buffer layer is located on first/second portions of the transparent substrate. The first/second gate patterns are formed on the buffer layer and located respectively on the first/second portions. The transparent insulating layer covers the first/second gate patterns and the buffer layer. The first/second polysilicon patterns are formed on the transparent insulating layer, and have neighboring first/second regions and neighboring third/fourth regions; the second/fourth regions are first/second lightly doped polysilicon regions respectively; the first region and the first gate pattern have an identical first patterning shape; and the third region and the second gate pattern have an identical second patterning shape. The array substrate has a simple process, low producing cost, and high product yield.