LTPS Array Substrate Symmetrical Low Doped Regions
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Solution Overview
Problem
Conventional array substrates for low temperature poly-silicon (LTPS) thin film transistor liquid crystal displays (TFT-LCDs) face misalignment issues during photolithography, leading to asymmetrical low doped regions, which increase leakage current and power consumption.
Innovation Solution
A manufacturing method that uses a mask plate to control exposure energy and achieve identical lengths for the low doped regions on both sides of the gate metal layer, ensuring symmetrical formation and reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two mask plates are used to perform photolithography to form gate electrode and low doped region, then the gate electrode and low doped region can be formed, but misalignment between mask plates causes asymmetrical low doped regions with different lengths
Solution Approach 1:
The patent combines the gate electrode formation and low doped region formation into a single photolithography step using one mask plate. The mask plate simultaneously defines both the gate electrode pattern and the low doped region pattern, eliminating misalignment issues between multiple mask plates while reducing process complexity.
Solution Approach 2:
The mask plate is designed with segmented functional zones: one zone for forming the gate electrode and another zone for forming the low doped regions. This segmentation allows both structures to be formed in one exposure step while maintaining precise spatial relationships, solving the alignment problem without increasing overall process complexity.
2Reliability
If asymmetrical low doped regions are formed, then the photolithography process is simpler, but the TFT's ability to suppress leakage current is reduced
Solution Approach 1:
By merging the pattern definition of gate electrode and low doped regions into a single mask plate, the patent ensures that both structures are formed with the same reference frame, guaranteeing symmetrical low doped regions that maintain equal length and properly suppress leakage current.
Solution Approach 2:
The mask plate design copies the symmetrical geometry of the gate electrode to the low doped region definition. The low doped regions are positioned symmetrically relative to the gate electrode centerline, ensuring identical lengths and proper electrical characteristics through geometric copying.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively suppresses leakage current and lowers power consumption in LTPS-TFT LCDs by ensuring the low doped regions are symmetrically formed, enhancing the TFT's ability to manage current.
Implementation Method 1
an excimer laser, used as a heat source, is projected onto an amorphous silicon structure prepared on a glass substrate. The amorphous silicon structure, after absorbing the energy of the excimer laser, is turned into a poly-silicon structure
Implementation Method 2
The amorphous silicon structure, after absorbing the energy of the excimer laser, is turned into a poly-silicon structure
Implementation Method 3
obtaining a second exposure feature size larger than the size of the gate metal layer by using the mask plate and controlling exposure energy, to form low doped regions located at opposite sides of the gate metal layer and having a same length
Data Source
AI summary
A method for manufacturing an array substrate comprising: using a mask plate (4), and controlling exposure energy to obtain a first exposure feature size, so as to form a gate metal layer on the array substrate; and using the mask plate again, and controlling exposure energy to obtain a second exposure feature size larger than a size of the gate metal layer, so as to form low doped regions (8) located at opposite sides of the gate metal layer and having a same length. The method can form the two low doped regions of the LTPS-TFT having the same length and guarantee the ability of the LTPS-TFT to suppress the leakage current.