LTPS Array Substrate Reducing Mask Count via Self-Aligned Fabrication
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Solution Overview
Problem
The fabrication of low-temperature poly-silicon thin film transistor array substrates is complex and productivity is hindered due to the high number of masks required, typically around ten, which complicates the process and reduces efficiency.
Innovation Solution
The array substrate design includes a low-temperature poly-silicon thin film transistor structure with a reduced number of masks, featuring a substrate with a low-temperature poly-silicon layer, source, drain, and conductive layers, along with insulating, gate, passivation, and ohmic contact layers, optimized to function with only seven masks, thereby simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the conventional low temperature poly-silicon thin film transistor fabrication process is used, then the transistor performance (electron mobility) is improved, but the number of masks required increases to ten, making the fabrication process complex and reducing productivity
Solution Approach 1:
The patent combines multiple mask steps into fewer steps by using self-aligned fabrication techniques. Specifically, the source and drain electrodes are formed in a single mask step, and the gate electrode is formed in another single mask step, reducing the total mask count from ten to seven while maintaining the low temperature poly-silicon transistor performance
Solution Approach 2:
The patent performs preliminary actions by forming the source and drain electrodes before the gate electrode, and using these previously formed structures as alignment references for subsequent steps. This self-aligned approach eliminates the need for additional masks that would otherwise be required for precise alignment, thereby reducing the total number of masks from ten to seven
2Productivity
If the number of masks is reduced to seven, then the fabrication process is simplified and productivity is improved, but the manufacturing precision and alignment accuracy must be maintained
Solution Approach 1:
The patent performs preliminary actions by forming the source and drain electrodes before the gate electrode, and using these previously formed structures as alignment references for subsequent steps. This self-aligned approach eliminates the need for additional masks that would otherwise be required for precise alignment, thereby reducing the total number of masks from ten to seven while maintaining manufacturing precision
Solution Approach 2:
The patent employs self-aligned fabrication where previously formed structures (source and drain electrodes) serve as their own alignment references for subsequent steps (gate electrode formation). This self-service mechanism ensures high alignment accuracy without requiring additional masks or complex alignment procedures, thus improving productivity while maintaining precision
Data Source
AI summary
The invention provides an array substrate, a display panel and a method for preparing an array substrate. The array substrate includes multiple low temperature poly-silicon (LTPS) thin film transistors arranged in an array. Each LTPS thin film transistor includes: a substrate; a LTPS layer, a source, a drain and a first conductive layer disposed on a same surface of the substrate, the source and the drain respectively being arranged at two sides of the LTPS layer and electrically connected with the LTPS layer, the drain being electrically connected with the first conductive layer; an insulating layer disposed on the LTPS layer, the source, the drain and the first conductive layer; a gate disposed on the insulating layer and corresponding to the LTPS layer; a passivation layer disposed on the gate; and a second conductive layer disposed on the passivation layer and corresponding to the first conductive layer.