LTPS CMOS Transistor Channel Doping via Light Shielding Pattern
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Solution Overview
Problem
The complexity of the low temperature polysilicon (LTPS) process for Complementary Metal Oxide Semiconductor (CMOS) transistors requires channel doping, which necessitates designing a specific exposure mask for the N-type channel region, increasing production costs.
Innovation Solution
A manufacturing method for CMOS transistors that uses a negative photoresist and a light shielding pattern as a mask for channel doping, eliminating the need for a custom exposure mask for the N-type channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a custom exposure mask is designed for the N-type channel region pattern, then the channel doping precision is improved, but the production cost increases
Solution Approach 1:
The invention uses the light shielding pattern as a template or copy to define the exposure area for the negative photoresist. Instead of creating a new custom mask, the existing light shielding pattern serves as the reference copy that determines the doping region, eliminating the need for separate mask design while maintaining precision
Solution Approach 2:
The light shielding pattern serves multiple functions: it acts as both the structural component for light shielding during transistor operation and as the exposure mask pattern during the doping process. This multi-functionality eliminates the need for dedicated custom masks, reducing production cost while maintaining doping precision
2Manufacturing precision
If a custom exposure mask is designed for each N-type channel region pattern, then the doping accuracy is improved, but the device complexity increases
Solution Approach 1:
The invention merges the light shielding pattern design with the exposure mask function. The same pattern that provides light shielding for transistor operation is combined with the mask function for doping, eliminating the need for separate custom mask designs and reducing overall process complexity
Solution Approach 2:
Instead of using a positive photoresist that requires light exposure to form the pattern (conventional approach), the invention uses negative photoresist where light exposure prevents pattern formation. This inversion allows the light shielding pattern to directly serve as the exposure template, simplifying the overall process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach saves production costs by eliminating the need for custom exposure mask design and simplifies the channel doping process for N-type channel regions in CMOS transistors.
Implementation Method 1
coating a negative photoresist on the substrate, and using the light shielding pattern as a mask to implement exposure to the negative photoresist from a back surface of the substrate to form a negative photoresist mask plate exposing the N-type channel region after development
Implementation Method 2
using the light shielding pattern as a mask to implement exposure to the negative photoresist from a back surface of the substrate
Data Source
AI summary
Disclosed is a manufacturing method of a complementary metal oxide semiconductor transistor, comprising a step of implementing a channel doping to an N-type channel region. The step comprises: preparing a low temperature polysilicon layer on a substrate, and patterning the low temperature polysilicon layer to form the N-type channel region correspondingly above a light shielding pattern; coating a negative photoresist on the substrate, and using the light shielding pattern as a mask to implement exposure to the negative photoresist from a back surface of the substrate to form a negative photoresist mask plate exposing the N-type channel region after development; implementing the channel doping to the N-type channel region with shielding of the negative photoresist mask plate. Further disclosed is a manufacturing method of an array substrate, applied with the aforesaid manufacturing method of the complementary metal oxide semiconductor transistor.