LTPS Array Substrate Gate Insulator Formation
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Solution Overview
Problem
The conventional manufacturing process of low temperature poly-silicon (LTPS) array substrates is complex, time-consuming, and costly due to the requirement of multiple film layers and chemical vapor deposition processes.
Innovation Solution
A simplified manufacturing method that reduces the number of chemical vapor deposition processes by forming the gate insulating and interlayer insulating layers in a single step, optimizing the process to decrease the thickness and production cost of the LTPS array substrate while maintaining the semiconductor device structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two times of chemical vapor deposition process are used to form gate insulator and interlayer dielectric separately, then the insulating layers are formed with proper structure, but the manufacturing process becomes complex and time-consuming
Solution Approach 1:
The patent combines the formation of gate insulator and interlayer dielectric into a single chemical vapor deposition process. The insulating layer is formed with a first region (gate insulator) and a second region (interlayer dielectric) in one continuous deposition step, eliminating the need for separate deposition processes and reducing manufacturing complexity while maintaining proper structural differentiation.
2Manufacturing precision
If two times of chemical vapor deposition process are used to form gate insulator and interlayer dielectric separately, then the insulating layers are formed with proper structure, but the manufacturing time increases
Solution Approach 1:
The patent merges two separate chemical vapor deposition processes into one continuous deposition process. The insulating layer is formed with differentiated first and second regions in a single CVD run, eliminating the time required for a second deposition cycle and associated processing steps, thereby reducing total manufacturing time while preserving structural integrity.
Solution Approach 2:
The patent performs preliminary patterning or positioning before the single chemical vapor deposition process to ensure that the first and second regions of the insulating layer are formed in their correct locations during one deposition cycle. This preliminary preparation enables the combined process to achieve proper structural differentiation without requiring multiple deposition steps.
3Reliability
If multiple film layers are used in LTPS array substrate, then the device structure is complete, but the production cost increases
Solution Approach 1:
The patent reduces the total number of deposition processes by combining gate insulator and interlayer dielectric formation into one chemical vapor deposition step. This merger maintains the complete device structure with properly differentiated insulating regions while reducing manufacturing steps, material waste, and production costs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces manufacturing steps and time, lowering production costs by forming the gate insulating and interlayer insulating layers in one-time chemical vapor deposition, resulting in a thinner and more cost-effective LTPS array substrate.
Implementation Method 1
forming the gate insulating and interlayer insulating layer through chemical vapor deposition on the polycrystalline silicon layer
Data Source
AI summary
A manufacturing method of a low temperature poly-silicon (LTPS) array substrate is described. The LTPS array substrate includes a metal light-shielding layer, a buffer layer, a polycrystalline silicon layer, a gate insulating and interlayer insulating layer, a gate line layer, and a source and drain electrode layer. The method adopts a one-time chemical vapor deposition process to form a gate insulator and interlayer insulating layer. A gate line trench is formed in the gate insulating layer and the interlayer insulating layer, thereby reducing the thickness of the LTPS array substrate film layer and the process steps.