LTPS Array Substrate Gate Electrode Transition Pattern
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Solution Overview
Problem
The existing preparation processes for LTPS thin film transistors suffer from significant doped area deviations due to inaccurate lengths of heavily and lightly doped areas, leading to poor electrical properties and reduced reliability and yield rates, primarily caused by limitations in photoresist blocking capacity and excessive photoresist loss during etching processes.
Innovation Solution
A method involving a combined wet etching and dry etching process to form a gate electrode transition pattern, followed by sequential doping to ensure accurate dimensions of heavily and lightly doped areas, utilizing the transition pattern as a shelter to prevent ion infiltration and minimize photoresist loss, thereby stabilizing the doped area lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional etching process is used to form the gate electrode pattern, then the photoresist blocking capacity is insufficient, but using a combined wet and dry etching process increases manufacturing precision
Solution Approach 1:
The etching process is divided into two distinct stages: first wet etching to remove 80-90% of the gate metal layer thickness, then dry etching to complete the pattern formation. This segmentation allows each process to be optimized independently, with wet etching providing high removal efficiency and dry etching providing precise dimensional control and photoresist protection.
Solution Approach 2:
The wet etching step is performed as a preliminary action before dry etching, pre-removing the majority of the metal layer thickness. This preliminary action reduces the burden on the subsequent dry etching process, allowing it to focus on achieving precise pattern definition with minimal photoresist loss.
2Reliability
If photoresist is used as a shelter during doping, then photoresist loss occurs during etching, but the gate electrode transition pattern provides better protection
Solution Approach 1:
The gate electrode transition pattern serves as an intermediary structure between the photoresist and the doping process. This transition pattern provides enhanced protection during doping while minimizing photoresist consumption during etching, as it is specifically designed with optimized dimensions and material properties.
Solution Approach 2:
The gate electrode transition pattern is formed with specific dimensional parameters (width and thickness) that are optimized to provide adequate doping protection while minimizing photoresist loss during etching. The parameters are carefully controlled to balance protection effectiveness with photoresist conservation.
3Manufacturing precision
If conventional doping processes are used, then doped area deviations occur, but sequential doping with transition pattern improves precision
Solution Approach 1:
The doping process is segmented into sequential heavy doping and light doping steps, with the gate electrode transition pattern formed in between. This segmentation allows precise control over the doped area dimensions by using the transition pattern as a defined boundary, eliminating the need for excessive photoresist margins.
Solution Approach 2:
The gate electrode transition pattern is formed as a preliminary structure before the doping process, establishing precise boundaries for the doped areas. This preliminary action enables accurate dimension control during subsequent doping without requiring large photoresist overhangs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively addresses the issue of doped area deviations, enhancing the electrical properties of LTPS thin film transistors and increasing the reliability and yield rate by ensuring precise doped area lengths and reducing photoresist loss, while also shortening etching time and minimizing damage to the gate insulating layer.
Implementation Method 1
etching the gate metal layer by using the wet etching process, to form an etched portion of the gate metal layer in which 80% to 90% of a thickness of the gate metal layer is removed
Implementation Method 2
further etching the gate metal layer by using the dry etching process, to remove the etched portion of the gate metal layer and a portion of the photoresist pattern beyond the width of non-etched portion of the gate metal layer
Implementation Method 3
doping an area of the active layer not sheltered by the gate electrode transition pattern with ions to form a heavily doped area of the active layer
Data Source
AI summary
The embodiments of the present disclosure provide an array substrate, a preparation method thereof, and a display device. The preparation method of an array substrate comprises: forming the active layer, a gate insulating layer, the gate metal layer and the patterned photoresist sequentially on a substrate; forming a gate electrode transition pattern by etching a gate metal layer via a patterned photoresist, using a wet etching process and a dry etching process sequentially; and doping an area of the active layer not sheltered by the gate electrode transition pattern with ions to form a heavily doped area of the active layer.