LTPS Array Substrate Groove Air Layer for Grain Boundary Control
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Solution Overview
Problem
Existing low-temperature polycrystalline silicon array substrates for display panels have a high number of grain boundaries in thin film transistors, leading to defects and instability in TFT output characteristics.
Innovation Solution
A manufacturing method involving a groove on the substrate with a buffer layer and air layer formation to improve heat dissipation, allowing for Excimer Laser Annealing that reduces grain boundaries by crystallizing silicon from the edges of source and drain electrodes towards the channel, enhancing grain size and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If ELA recrystallization is used to form polycrystalline silicon, then the manufacturing process is simple, but the number of grain boundaries increases and TFT output characteristics deteriorate
Solution Approach 1:
The patent introduces a heat dissipation structure (convex portion or protrusion) at specific locations (source and drain electrode regions) to create localized heat dissipation channels. This causes different cooling rates in different regions: the source/drain regions cool faster while the channel region cools slower, leading to controlled crystallization that reduces grain boundaries in the channel while maintaining manufacturing simplicity
Solution Approach 2:
The heat dissipation structure is formed in advance before the ELA process. This preliminary structure preparation ensures that during laser annealing, heat is automatically directed to specific regions, guiding the crystallization process to start from source/drain edges and grow toward the channel, thereby reducing grain boundaries before they can form disorderly
2Productivity
If amorphous silicon is deposited and recrystallized through ELA, then the polycrystalline silicon is formed efficiently, but grain boundaries are distributed disorderly in the channel
Solution Approach 1:
By creating localized heat dissipation paths through the convex portion structure, the patent achieves different thermal histories in different regions. The source and drain regions with heat dissipation structures cool faster, while the channel region cools slower, enabling controlled grain growth direction and reducing disorderly grain boundary distribution while maintaining high formation efficiency
Solution Approach 2:
The heat dissipation structure acts as an intermediary element that mediates the thermal field during ELA. It controls heat flow direction and cooling rate, serving as a template that guides crystallization to proceed from source/drain edges toward the channel, thereby controlling grain boundary distribution without compromising formation efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method reduces the number of grain boundaries in the polycrystalline silicon active layer, improving the work stability and output characteristics of thin film transistors by controlling grain boundary direction and size.
Implementation Method 1
the buffer layer covers a surface of the groove to form an air layer in the groove
Implementation Method 2
melting and recrystallizing an amorphous silicon deposited on a substrate through Excimer Laser Anneal (ELA)
Implementation Method 3
the amorphous silicon layer at the source and drain electrode regions of the thin film transistor will be firstly cured and crystallized to make the molten silicon start to be crystallized from an edge of the source and drain electrodes
Data Source
AI summary
The present disclosure provides a low-temperature polycrystalline silicon array substrate which includes a substrate, a groove disposed on the substrate, a buffer layer disposed on the substrate, and a polycrystalline silicon active layer disposed on the buffer layer, the groove is located at a channel of a thin film transistor, and the buffer layer covers the groove to form an air layer in the groove. The present disclosure further provides a manufacturing method of a low-temperature polycrystalline silicon array substrate, mainly including: manufacturing a groove at a channel of a thin film transistor on a substrate; depositing a metal sacrificial layer on the substrate, and etching the metal sacrificial layer except the groove through an etching process; sequentially forming a buffer layer and an amorphous silicon layer on the substrate; and removing the metal sacrificial layer in the groove to form an air layer in the groove.