LTPS Array Substrate Halftone Mask Doping Integration
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Solution Overview
Problem
The manufacture process of LTPS array substrates is complex and costly due to the need for multiple photolithographic masks and processes in channel and heavy doping steps, which increases production costs and complexity.
Innovation Solution
A method that integrates the N type heavy doping and channel doping of the NMOS region and P type heavy doping of the PMOS region into a single halftone mask process, reducing the number of masks required and eliminating two exposure processes, utilizing low temperature crystallization and specific doping ions, and employing dry etching and photoresist stripping to achieve doping regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple photolithographic masks and processes are used for channel doping and heavy doping steps, then doping precision and device performance are improved, but manufacturing complexity and production cost increase
Solution Approach 1:
The patent combines three separate photolithographic mask processes (channel doping mask, N-type heavy doping mask, and P-type heavy doping mask) into a single integrated mask structure. This mask contains multiple patterned regions that enable all three doping operations to be performed simultaneously in one exposure step, thereby reducing manufacturing complexity while maintaining doping precision through the carefully designed pattern geometry
Solution Approach 2:
The integrated mask serves multiple functions: it defines channel doping regions, N-type heavy doping regions, and P-type heavy doping regions all in one component. This multi-functional mask eliminates the need for separate masks for each doping operation, reducing the total number of photolithographic steps while ensuring precise alignment through the unified mask structure
2Manufacturing precision
If multiple photolithographic masks are used for doping processes, then doping accuracy is improved, but production cost increases
Solution Approach 1:
By merging three separate mask processes into one integrated mask, the patent reduces material costs (fewer masks to purchase and store), labor costs (fewer mask alignment and exposure operations), and time costs (reduced total exposure time). The single mask maintains doping accuracy through its precisely engineered pattern that defines all doping regions simultaneously
Solution Approach 2:
The integrated mask creates a single exposure that simultaneously patterns all three doping regions (channel, N-type heavy, P-type heavy) in one photolithographic step. This copying approach replicates all necessary doping patterns in a single operation, eliminating the need for multiple sequential mask operations and associated costs
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the manufacturing cost and complexity by integrating three processes into one mask process, raising exposure capacity and resulting in a LTPS array substrate with great electrical properties.
Implementation Method 1
employing a low temperature crystallization process to convert the amorphous silicon layer into the polysilicon layer
Implementation Method 2
after employing a halftone mask to implement exposure, development to the photoresist layer, forming first vias corresponding to two ends of the second polysilicon layer in the photoresist layer
Implementation Method 3
employing the photoresist layer to be a mask to implement P type heavy doping to the two ends of the second polysilicon layer
Implementation Method 4
employing a dry etching process to implement ashing treatment to the photoresist layer to decrease a thickness of the photoresist layer to make the first grooves converted into second vias
Data Source
AI summary
The present invention provides a manufacture method of a LTPS array substrate. By utilizing one halftone mask, the N type heavy doping, the channel doping of the first polysilicon layer of the NMOS region and the P type heavy doping of the second polysilicon layer of the PMOS region, the three processes which previously require three masks are integrated into one mask process, and two exposure processes are eliminated, which significantly raises the exposure capacity, and meanwhile saves the manufacture cost of two masks to effectively reduce the manufacture cost of the LTPS array substrate, and the manufactured LTPS array substrate possesses great electrical property.