LTPS Array Substrate PMOS Hot Carrier Alleviation
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Solution Overview
Problem
Current Low Temperature Poly-silicon (LTPS) technology fails to effectively alleviate the hot carrier effect in PMOS transistors, which affects the off-state current of Thin Film Transistors (TFTs), while existing methods only reduce the hot carrier effect in NMOS transistors.
Innovation Solution
A method for manufacturing a low temperature polysilicon array substrate involves forming a light shield layer, a buffer layer, and doping channels and areas on a glass substrate using specific masks and doping processes to create NMOS and PMOS channels, source, and drain areas, with P− light doping and P+ heavy doping to alleviate the hot carrier effect in PMOS transistors without adding additional masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional masks are added to perform P- light doping on PMOS areas, then hot carrier effect in PMOS transistor can be alleviated, but device complexity and manufacturing process complexity increase
Solution Approach 1:
The patent combines multiple doping operations into unified processing steps. Specifically, it merges the formation of N-type LDD regions and P-type LDD regions into coordinated doping processes that share common process steps and masks where possible, thereby achieving differentiated doping for both transistor types without proportionally increasing the total number of masks and process complexity.
Solution Approach 2:
The patent designs doping masks and process sequences that serve multiple functions. For example, certain masks are configured to perform both NMOS channel definition and PMOS LDD doping in coordinated steps, allowing a single mask structure to fulfill multiple roles in the fabrication process, thus avoiding the need for separate dedicated masks for each doping operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively alleviates the hot carrier effect in PMOS transistors, improving the performance of the array substrate by reducing the hot carrier effect without increasing the number of masks used in the manufacturing process.
Implementation Method 1
depositing a monocrystalline silicon material on the buffer layer, and treating the monocrystalline silicon material to form a polysilicon island
Implementation Method 2
doping a channel of an NMOS area of the polysilicon island and performing P− light doping on two areas at two sides of a PMOS area of the polysilicon island
Data Source
AI summary
A low temperature polysilicon array substrate and a method for manufacturing the same are disclosed. The method includes forming a light shield layer, a buffer layer, and a polysilicon island on a glass substrate in sequence, performing channel doping on an NMOS area of the polysilicon island, performing P− light doping on two sides of a PMOS area of the polysilicon island, performing N+ heavy doping, forming a gate insulating layer and a gate layer, and performing N− light doping and P+ heavy doping.