LTPS Array Substrate Seed Layer for Lower-Resistivity Mo Wiring
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Solution Overview
Problem
The high resistivity of molybdenum (Mo) metal in the first metal layer wire of low-temperature poly-silicon (LTPS) TFT display products restricts high charging rates and high-frequency performance due to its high impedance, which is disadvantageous for high-resolution and middle-size display products.
Innovation Solution
An array substrate with a seed layer, where the first metal layer directly contacts the seed layer, inducing metal crystallization to form larger grains with fewer grain boundaries and lower charge carrier scattering, thereby reducing the resistivity of the first metal layer without increasing the number of masks or modifying equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If molybdenum (Mo) metal is used to form the first metal layer wire, then high-temperature resistance is maintained, but resistivity is high which restricts high charging rate and high-frequency performance
Solution Approach 1:
A seed layer is introduced as an intermediary between the underlay and the first metal layer. This seed layer has a lattice structure that matches the first metal layer, facilitating metal crystallization and grain growth. The seed layer acts as a mediator that enables the first metal layer to achieve larger grain sizes and lower resistivity while maintaining high-temperature resistance properties
Solution Approach 2:
The invention changes the lattice structure parameters of the first metal layer by using a seed layer with a specific lattice constant that matches or is close to the first metal layer. This parameter matching promotes epitaxial growth and crystallization, transforming the metal layer from a fine-grained structure to a coarse-grained structure with lower resistivity
2Manufacturing precision
If the first metal layer is formed with fine grains, then manufacturing precision is maintained, but grain boundaries increase causing higher charge carrier scattering and resistivity
Solution Approach 1:
The seed layer is prepared in advance before forming the first metal layer. This preliminary action establishes a template with the desired lattice structure and grain orientation, guiding the subsequent metal deposition to grow with larger grains and fewer boundaries, thereby reducing charge carrier scattering before the actual metal layer formation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution decreases the resistivity of the first metal layer by 30% while maintaining high-temperature resistance, enhancing the performance of medium and large-size display products and improving the competitiveness of the display panel.
Implementation Method 1
The present application utilizes the seed layer directly contacting the first metal layer to induce the metal crystallization of the first metal layer
Implementation Method 2
a lattice structure of the first metal layer is the same as a lattice structure of the seed layer
Data Source
AI summary
An array substrate and a display panel are disclosed. The array substrate includes an underlay, a seed layer disposed on one side of the underlay, and a first metal layer disposed on one side of the seed layer and away from the underlay, wherein the first metal layer directly contacts the seed layer. The present application utilizes the seed layer directly contacting the first metal layer to induce crystallization of the first metal layer, so that the first metal layer is formed with larger grains, fewer grain boundaries and less charge carrier scattering, and a resistivity of the first metal layer is decreased.