LTPS Thin Film Transistor Active Layer Thickness Profile
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Solution Overview
Problem
Low-temperature poly-silicon thin film transistors (LTPS TFTs) face issues with unsatisfactory ohmic contact between the source and drain and the active layer, leading to high contact resistance and device degradation, especially in flexible devices where the poly silicon layer is prone to piercing during through-hole formation.
Innovation Solution
The method involves forming source-and-drain-to-be-formed regions of the active layer thicker than the semiconductor region between them, and using a patterning process to create grooves for the source and drain, ensuring electrical connection and preventing poly silicon etching through, thus enhancing contact area and reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through holes are formed in the source-and-drain-to-be-formed regions to create source and drain patterns, then electrical connection is achieved, but the poly silicon layer is pierced leading to small contact area and large contact resistance
Solution Approach 1:
The patent applies local quality by creating a non-uniform active layer thickness profile where the source-and-drain-to-be-formed regions have greater thickness than the semiconductor region between them. This localized thickness variation ensures that when through holes are formed, the poly silicon layer is not pierced in the source and drain regions, maintaining adequate contact area and reducing contact resistance while still achieving electrical connection.
2Ease of manufacture
If the poly silicon layer is pierced during through hole formation, then source and drain patterns are created, but contact resistance increases significantly
Solution Approach 1:
The patent uses local quality by making the active layer thickness non-uniform, specifically thicker in the source-and-drain-to-be-formed regions. This localized thickness increase prevents complete piercing of the poly silicon layer during through hole formation, thereby maintaining low contact resistance while still allowing the patterning process to create the necessary source and drain structures.
3Adaptability or versatility
If low annealing temperature is used for flexible devices, then substrate flexibility is maintained, but ohmic contact quality deteriorates due to insufficient contact area
Solution Approach 1:
The patent applies local quality by creating thicker active layer regions specifically at the source and drain areas. This localized thickness enhancement compensates for the low annealing temperature in flexible devices by ensuring adequate contact area between the source/drain electrodes and the active layer, thereby maintaining good ohmic contact quality while preserving substrate flexibility.
Data Source
AI summary
A thin film transistor, a method for fabricating the same, an array substrate, and a display device are provided. The method comprises forming an active layer on a substrate, wherein source-and-drain-to-be-formed regions of the active layer are thicker than a semiconductor region between the source-and-drain-to-be-formed regions, and by a patterning process, forming a gate on the active layer, and forming a pattern of source and drain in the source-and-drain-to-be-formed regions of the active layer.