LTPS TFT Dual Gate Structure for Photo Leakage Control
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Solution Overview
Problem
Conventional LTPS TFTs suffer from photo leakage current on channels without shielding layers, leading to poor yield rates and reliability issues in CMOS circuit manufacturing.
Innovation Solution
A dual-gate structure is implemented using a patterned a-Si layer as the bottom gate and a patterned GE layer as the top gate, eliminating the need for gate over wet etching and enhancing the I-V characteristic, breakover current, and driving capability, while increasing yield rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional top gate structure is used in LTPS TFT, then the manufacturing process is simple, but photo leakage current easily occurs on channels when LCD shows images without shielding layers
Solution Approach 1:
The gate structure is segmented into two independent gates: a bottom gate (a-Si layer) and a top gate (GE layer). This segmentation allows each gate to perform specific functions - the bottom gate provides shielding against photo leakage while the top gate controls channel formation, resolving the contradiction between manufacturing simplicity and photo leakage resistance
Solution Approach 2:
The top gate electrode is nested above the bottom gate structure, forming a dual-gate configuration where the top gate is positioned over the channel region formed by the bottom gate. This nested arrangement enables effective photo leakage shielding while maintaining compact device structure and reasonable manufacturing complexity
2Ease of manufacture
If gate over wet etching process is used in CMOS manufacturing, then mask is not necessary, but yield rate is poor
Solution Approach 1:
The bottom gate (a-Si layer) is formed and patterned in advance before the top gate electrode is deposited. This preliminary action creates a defined channel region that guides subsequent top gate formation, eliminating the need for gate over wet etching while ensuring high alignment precision and yield rate
Solution Approach 2:
The bottom gate structure serves dual purposes: it acts as the control gate for channel formation and simultaneously serves as a shielding layer against photo leakage. This self-service function eliminates the need for additional masking steps and gate over etching processes, improving both manufacturing ease and yield rate
Data Source
AI summary
The present invention proposes a low temperature poly-silicon thin-film transistor having a dual-gate structure and a method for forming the low temperature poly-silicon thin-film transistor. The low temperature poly-silicon thin-film transistor includes: a substrate, one or more patterned amorphous silicon (a-Si) layers, disposed in a barrier layer on the substrate, for forming a bottom gate, an NMOS disposed on the barrier layer, and a PMOS disposed on the barrier layer. The NMOS comprises a patterned gate electrode (GE) layer as a top gate, and the patterned GE layer and the bottom gate formed by the one or more patterned a-Si layers form a dual-gate structure. The present invention proposes a low temperature poly-silicon thin-film transistor with a more stabilized I-V characteristic, better driving ability, low power consumption, and higher production yield.