LTPS TFT Active Layer Patterning for Larger Poly-Silicon Grains
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Solution Overview
Problem
Conventional methods for manufacturing LTPS TFTs using Excimer Laser Annealing result in small grain size p-Si with high grain boundaries, leading to undesirably high leakage currents due to limited adjustable process window and short heat retaining duration.
Innovation Solution
A method involving the formation of a function layer on the amorphous silicon layer, which has a different heat retaining duration and pressure in covered and uncovered portions, allowing for larger grain sizes in poly-silicon and reducing leakage currents without additional masks or compromising production efficiency, using a non-metal material like silicon oxide or nitride for the function layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional ELA process is used to crystallize a-Si layer, then manufacturing process is simple, but grain size of p-Si is small and grain boundaries are numerous
Solution Approach 1:
The patent applies local quality by forming a first dielectric layer in a first region of the substrate that corresponds to a first portion of the a-Si layer, while leaving a second region without the dielectric layer. This creates different thermal environments in different regions during laser annealing, allowing the first portion to develop larger grain sizes with fewer grain boundaries while maintaining process simplicity.
2Ease of manufacture
If ELA process with limited adjustable window is used, then manufacturing is straightforward, but heat retaining duration is short leading to high leakage currents
Solution Approach 1:
The patent applies preliminary action by forming the first dielectric layer before the laser annealing process. This dielectric layer serves as a heat retaining structure that prolongs the heat retaining duration during subsequent laser annealing, enabling better crystallization and reducing leakage currents without complicating the overall manufacturing approach.
3Manufacturing precision
If additional masks or process steps are added to increase grain size, then grain boundaries reduce, but production efficiency decreases
Solution Approach 1:
The patent merges the heat retaining function with the existing dielectric layer structure by forming the first dielectric layer in a specific region during the standard manufacturing process. This integration allows the layer to serve dual purposes: as part of the device structure and as a heat retaining element that promotes larger grain sizes, thereby reducing grain boundaries without adding separate process steps or masks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method results in TFTs with fewer grain boundaries, higher carrier mobility, and lower leakage currents, improving electrical properties and production efficiency.
Implementation Method 1
the a-Si layer undergoes a crystallization process through an ELA (Excimer Laser Annealing) process
Implementation Method 2
performing a crystallization process for converting the amorphous silicon layer to a poly-silicon layer
Implementation Method 3
forming a function layer on the amorphous silicon layer... having a different heat retaining duration and pressure in covered and uncovered portions
Data Source
Figure 1~2A
Figure 2B~2E
Figure 3
AI summary
A method for forming an active layer (3) with a pattern is provided. The method includes forming an amorphous silicon layer (31) and forming a function layer (4) on the amorphous silicon layer (31). The function layer (4) has a same pattern as the active layer (3). The method further includes performing a crystallization process for converting the amorphous silicon layer (31) to a poly-silicon layer (32). The poly-silicon layer (32) has first portions covered by the function layer (4) and second portions not covered by the function layer (4), and grain sizes of the poly-silicon in the first portions are larger than grain sizes of the poly-silicon in the second portions.