LTPS Thin Film Transistor Manufacturing via Metal-Induced Crystallization
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Solution Overview
Problem
Current manufacturing processes for low-temperature poly silicon thin film transistors are complex and costly due to the high number of photolithography steps required, which complicates the production cycle and increases costs.
Innovation Solution
A method involving the formation of a buffer and active layers on a substrate, followed by metal-induced lateral crystallization of amorphous silicon to poly silicon, reducing the number of photolithography steps to 5, and using a low-temperature poly silicon gate electrode to improve interface quality and reduce leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional manufacturing processes for low-temperature poly silicon thin film transistors are used, then the transistors achieve high carrier mobility and fast response speed, but the processes become complex and costly due to requiring 6 or more photolithography steps
Solution Approach 1:
The patent combines multiple photolithography steps into fewer steps by using a dual-gate structure where the first and second gate electrodes are formed in the same planarization layer. The source and drain regions are doped simultaneously to form both source and drain contacts in one doping step, reducing the total number of photolithography steps from 6 or more to just 3 steps, thereby simplifying the manufacturing process while maintaining high carrier mobility
Solution Approach 2:
The planarization layer serves multiple functions: it planarizes the substrate surface, forms the gate insulating layer, and serves as the gate electrode structure. This multi-functional design eliminates the need for separate layers and processing steps, reducing process complexity while maintaining device performance
2Manufacturing precision
If more photolithography steps are used to manufacture low-temperature poly silicon thin film transistors, then manufacturing precision can be improved, but the production cycle becomes longer and manufacturing costs increase
Solution Approach 1:
The patent performs preliminary doping of the semiconductor layer to form both source and drain regions before forming the gate electrodes. This preliminary action allows subsequent processing steps to focus only on gate formation and planarization, rather than requiring separate doping steps for source and drain, thereby reducing the production cycle while maintaining manufacturing precision
Solution Approach 2:
Multiple functions are merged into single processing steps: the same planarization layer forms both gate insulating and gate electrode structures, and a single doping step creates both source and drain regions. This merging reduces the number of sequential steps from 6 or more to just 3, significantly shortening the production cycle while maintaining structural precision
3Power
If conventional manufacturing processes are used, then sufficient drive current can be provided, but the manufacturing cost increases due to complex processes and high number of photolithography steps
Solution Approach 1:
The patent merges multiple processing steps into fewer steps: dual gate electrodes are formed in the same planarization layer, and source/drain regions are doped simultaneously. This reduces the number of photolithography steps from 6 or more to just 3 steps, directly lowering manufacturing costs while maintaining the high drive current capability through the dual-gate structure that provides sufficient control over the channel
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the processing procedure, reduces production costs, and enhances device performance by lowering the threshold voltage and leakage current, making it suitable for AMOLED and LTPS-LCD applications.
Implementation Method 1
crystallizing the amorphous silicon thin film material of both the active layer and the gate electrode into poly silicon thin film material by utilizing a metal-induced lateral crystallization method
Implementation Method 2
depositing metal Ni in the openings for Ni deposition and on the gate electrode
Data Source
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AI summary
Embodiments of the invention provide a thin film transistor, an array substrate, and a manufacturing method thereof The manufacturing method comprises: forming a buffer layer and an active layer sequentially on a substrate, and forming an active region through a patterning process; forming a gate insulating layer and a gate electrode sequentially; forming Ni deposition openings; forming a dielectric layer having source/drain contact holes in a one-to-one correspondence with the Ni deposition openings; and forming source/drain electrodes which are connected with the active region via the source/drain contact holes and the Ni deposition openings.