LTPS TFT Array Substrate with Multi-Gate and Low-k Resin

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Solution Overview

Problem

The high leakage current in low-temperature polysilicon (LTPS) structures, caused by metal gate materials, leads to reduced driving voltage stability and undesirable display performance, while dual-gate or multi-gate structures used to mitigate this issue compromise the display aperture ratio due to light blocking.

Innovation Solution

A low-temperature polysilicon thin film transistor array substrate with a multi-gate structure positioned directly below the source and a resin layer with a low dielectric constant between the gate and source/drain to reduce leakage current and improve aperture ratio, avoiding coupling capacitance and light blocking.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dual-gate or multi-gate structure is used to reduce leakage current, then leakage current is reduced, but aperture ratio deteriorates due to light blocking by metal gate material

Engineering Contradiction:
Improveleakage currentVSAvoidaperture ratio
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent changes the optical property of the gate electrode by using a transparent conductive oxide material instead of traditional metal material. This allows the gate to maintain its electrical function while becoming optically transparent, thus resolving the contradiction between reducing leakage current (through multi-gate structure) and maintaining aperture ratio (by eliminating light blocking).

Inventive Principle:
Principle #32Color changes

Solution Approach 2:

The patent employs composite material strategy by using transparent conductive oxide materials (such as ITO, IZO, or IGZO) which combine the properties of transparency and electrical conductivity. This composite material approach enables the gate electrode to simultaneously achieve low leakage current control and high aperture ratio by being both electrically functional and optically transparent.

Inventive Principle:
Principle #40Composite materials

2Productivity

If gate and source are positioned close to each other for compact design, then device integration is improved, but coupling capacitance increases causing leakage current

Engineering Contradiction:
Improvedevice integrationVSAvoidleakage current
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces a resin layer as an intermediary substance between the gate electrode and the source electrode. This resin layer with low dielectric constant acts as a mediator that reduces the coupling capacitance between the closely positioned gate and source, thereby reducing leakage current while maintaining compact device integration.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the dielectric parameter of the insulation layer by using a resin material with low dielectric constant between the gate and source. This parameter change reduces the coupling capacitance formed by the overlapping gate and source electrodes, thereby reducing leakage current while maintaining close positioning for compact integration.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces leakage current and enhances the aperture ratio of the display panel by positioning the multi-gate structure below the source and using a low dielectric resin layer, thereby improving display performance.

Implementation Method 1

the resin layer with low dielectric constant is provided between the gate and the source and drain, so that the coupling capacitance generated by the gate and the source overlapped with each other is avoided

Methodology Applied
Scientific EffectDielectric constant: Dielectric Permittivity

Data Source

PatentEP3163620B1Low temperature poly-silicon thin film transistor array substrate and manufacturing method therefor and display device
Publication Date: 2020.05.06 BOE TECHNOLOGY GROUP CO LTD
  • EP3163620B1 patent drawingFigure 1
  • EP3163620B1 patent drawingFigure 2A~2B
  • EP3163620B1 patent drawingFigure 3A~4B

AI summary

The present invention provides a low-temperature polysilicon thin film transistor array substrate and a method of fabricating the same, and a display device. The array substrate comprises: a substrate; a polysilicon active layer provided on the substrate; a first insulation layer provided on the active layer; a plurality of gates and a gate line provided on the first insulation layer; a second insulation layer provided on the gates; a source, a drain, a data line and a pixel electrode electrically connected with the drain, which are provided on the second insulation layer, the source covers the plurality of gates. The plurality of gates are provided directly below the source, so that the leakage current is reduced and the aperture ratio of panel is improved.