LTPS TFT Substrate Grain Control via Silicon Oxide Photomask
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Solution Overview
Problem
Conventional low temperature poly-silicon (LTPS) TFT substrate formation methods result in poorer uniformity and lower-than-expected electron mobility in the display and drive areas, affecting the overall quality of the substrate.
Innovation Solution
A method involving the deposition of a silicon oxide layer on the a-Si layer, which acts as a photomask during annealing with excimer laser, allowing for the formation of larger poly-Si grains in the drive area and smaller, more uniform grains in the display area, enhancing electron mobility and electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional LTPS TFT substrate formation method is used, then the substrate can be manufactured with standard processes, but the uniformity in the display area deteriorates and electron mobility in the drive area is lower than expected
Solution Approach 1:
The patent applies local quality by depositing a silicon oxide layer selectively in the display area to create different crystallization conditions in different regions. The silicon oxide layer modifies the laser annealing effect locally, resulting in smaller, more uniform grains in the display area while the drive area develops larger grains for higher electron mobility, thus resolving the contradiction between uniformity and electron mobility across different areas.
2Reliability
If silicon oxide layer is deposited on a-Si layer and annealed with excimer laser, then larger poly-Si grains are formed in drive area with higher electron mobility, but the process complexity increases
Solution Approach 1:
The silicon oxide layer serves as an intermediary material that mediates the laser annealing process. It absorbs and modulates the laser energy, creating the desired crystallization effect in the drive area without requiring complex process equipment or multiple processing steps. This intermediary approach achieves high electron mobility through a relatively simple additional deposition and annealing sequence.
3Manufacturing precision
If uniform small grains are formed in display area, then electrical property uniformity improves, but electron mobility is reduced compared to large grains
Solution Approach 1:
The patent segments the substrate into two distinct functional areas with different grain structures: the display area with small, uniform grains for electrical uniformity, and the drive area with large grains for high electron mobility. This segmentation is achieved through selective silicon oxide layer deposition and laser annealing, allowing each area to be optimized for its specific function without compromising the other.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the uniformity and electron mobility in the display area while maintaining high electron mobility in the drive area, resulting in a higher-quality LTPS TFT substrate with better electrical properties.
Implementation Method 1
anneal the a-Si layer with excimer laser
Implementation Method 2
the a-Si layer is turned into a poly-Si layer
Implementation Method 3
deposit a silicon oxide layer on the a-Si layer, and patterning the silicon oxide layer... which acts as a photomask during annealing with excimer laser
Data Source
AI summary
A method of forming an LTPS TFT substrate includes: Step 1: providing a substrate and depositing a buffer layer; Step 2: depositing an a-Si layer; Step 3: depositing and patterning a silicon oxide layer; Step 4: taking the silicon oxide layer as a photomask and annealing the a-Si layer with excimer laser, so that the a-Si layer crystalizes and turns into a poly-Si layer; Step 5: forming a first poly-Si region and a second poly-Si region; Step 6: defining a heavily N-doped area and a lightly N-doped area on the first and second poly-Si regions, and forming an LDD area; Step 7: depositing and patterning a gate insulating layer; Step 8: forming a first gate and a second gate; Step 9: forming via holes; and Step 10: forming a first source/drain and a second source/drain.


