LTPS TFT Display Device Single Mask Photolithography Process
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Solution Overview
Problem
The manufacturing process of large-sized display devices, particularly those using low-temperature polycrystalline silicon thin film transistors (LTPS TFTs), is hindered by the increasing number of masks required, leading to reduced productivity.
Innovation Solution
A display device structure and manufacturing method that simplifies the process by using a single mask for photolithography to pattern the polycrystalline silicon film, gate insulating layer, and first conductive film, with additional layers and doping techniques to reduce the number of necessary masks and steps, including the use of impurities like aluminum and a dual-exposure photolithography process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the number of masks is increased to manufacture large-sized display devices with LTPS TFTs, then the manufacturing precision and device performance are improved, but the productivity is reduced and manufacturing time is increased
Solution Approach 1:
The patent combines multiple mask patterns into a single mask by strategically designing the mask structure to include both the gate electrode pattern and the active layer pattern. This merging of multiple patterning steps into one simultaneous exposure process reduces the total number of masks from multiple to just one, thereby maintaining manufacturing precision while significantly improving productivity and reducing manufacturing time for large-sized display devices
Solution Approach 2:
The single mask designed in this patent serves multiple functions: it simultaneously defines the gate electrode regions, the active layer regions, and the capacitor electrode regions. This multi-functional mask design eliminates the need for separate masks for each component, resolving the contradiction between achieving precise multi-component patterning and maintaining high productivity
2Reliability
If the number of thin film processes is increased to manufacture LTPS TFTs, then the device performance and carrier mobility are improved, but the manufacturing complexity and time are increased
Solution Approach 1:
The patent performs preliminary doping of the semiconductor layer with impurities before the crystallization process. This preliminary action ensures that the semiconductor layer has the appropriate carrier concentration and electrical properties before forming the LTPS TFT structure, thereby maintaining high carrier mobility and device performance while reducing the need for subsequent complex doping processes that would increase manufacturing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the complexity and time required for manufacturing, enhancing productivity and allowing for the efficient production of large-scale display devices while maintaining a simple structure and achieving a mirror effect through interlayer insulating layers with different refractive indices.
Implementation Method 1
patterning the polycrystalline silicon film, the gate insulating layer, and the first conductive film through a photolithography process using a single mask
Implementation Method 2
Impurities may be doped on the polycrystalline silicon film pattern exposed through the plurality of second contact holes
Implementation Method 3
achieving a mirror effect through interlayer insulating layers with different refractive indices
Data Source
AI summary
A display device includes a substrate, a first conductive film pattern including a gate electrode and a first capacitor electrode on the substrate, a gate insulating layer pattern on the first conductive film pattern, a polycrystalline silicon film pattern including an active layer and a second capacitor electrode on the gate insulating layer pattern, an interlayer insulating layer on the polycrystalline silicon film pattern, a plurality of first contact holes through the gate insulating layer pattern and the interlayer insulating layer to expose a portion of the first conductive film pattern, a plurality of second contact holes through the interlayer insulating layer to expose a portion of the polycrystalline silicon film pattern, and a second conductive film pattern including a source electrode, a drain electrode, and a pixel electrode on the interlayer insulating layer.