LTPS-TFT Fabrication via Single Patterning and Dual Doping
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Solution Overview
Problem
Conventional methods for fabricating Low Temperature Poly-Silicon Thin Film Field Effect Transistor (LTPS-TFT) array substrates require multiple doping and patterning processes, leading to increased complexity, time, and cost due to high material consumption and leakage current issues.
Innovation Solution
A method involving a single patterning process to form semiconductor active islands with multiple pattern types, followed by dual doping processes to achieve desired conductivity types, reducing the overall number of patterning and doping steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple doping and patterning processes are used to solve leakage current issues in LTPS-TFTs, then the leakage current is reduced, but the fabrication process complexity increases, fabrication time increases, and material consumption increases
Solution Approach 1:
The patent combines multiple doping processes into a single doping step by using a multi-layer mask structure that defines all doping regions simultaneously. This merging approach reduces the number of separate doping and patterning steps while maintaining the ability to create different conductivity types in different regions, thereby reducing fabrication complexity without compromising leakage current control.
Solution Approach 2:
The patent segments the mask into multiple functional layers, where each layer serves a specific purpose in defining different doping regions. This segmentation allows complex doping patterns to be achieved in a single step, resolving the contradiction between achieving precise doping control and reducing process complexity.
2Reliability
If multiple doping and patterning processes are used to solve leakage current issues in LTPS-TFTs, then the leakage current is reduced, but the fabrication time increases
Solution Approach 1:
The patent merges multiple sequential doping operations into a single parallel doping process by using a multi-layer mask that exposes all required doping regions simultaneously. This eliminates the time required for repeated mask alignment, removal, and re-application, significantly reducing total fabrication time while maintaining precise doping control for leakage current management.
3Reliability
If multiple doping and patterning processes are used to solve leakage current issues in LTPS-TFTs, then the leakage current is reduced, but material consumption increases
Solution Approach 1:
The patent combines multiple doping steps into one, which directly reduces the consumption of dopant materials that would otherwise be used in each separate doping process. The multi-layer mask enables all necessary doping regions to be defined and processed in a single operation, minimizing material waste.
4Manufacturing precision
If multiple patterning processes are used to define different doping regions, then precise doping control is achieved, but the number of process steps increases
Solution Approach 1:
The patent segments the patterning function across multiple mask layers, where each layer contributes to defining specific doping regions. This segmentation allows precise control over different doping areas to be achieved within a single doping process step, eliminating the need for multiple sequential patterning operations while maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process, decreases material consumption, and lowers fabrication costs while maintaining high electron mobility and resolution in LTPS-TFTs.
Implementation Method 1
doping a semiconductor at the second patterns for once to form a semiconductor of a first conductivity type; and doping a semiconductor at the third patterns for once to form a semiconductor of a second conductivity type
Data Source
AI summary
Embodiments of the invention provides a method for fabricating an array substrate comprising: forming, on a substrate, at least two semiconductor active islands, first patterns positioned on both sides of each of the semiconductor active islands, second patterns positioned at outer side of a part of the first patterns, and third patterns positioned at outer side of the rest of the first patterns, through a single patterning process; doping a semiconductor at the second patterns for once to form a semiconductor of a first conductivity type; and doping a semiconductor at the third patterns for once to form a semiconductor of a second conductivity type.