LTPS Thin-Film Transistor Doping via Low-Temperature Laser Crystallization
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Solution Overview
Problem
Conventional low-temperature polycrystalline silicon (LTPS) thin film transistors experience high leak currents due to ion implantation at high temperatures, which causes thermal damage to flexible substrates like polyimide, making it difficult to achieve satisfactory dopant diffusion without damaging the base substrate.
Innovation Solution
A method is developed to fabricate LTPS thin film transistors by forming amorphous silicon layers on a base substrate, followed by crystallization using excimer laser annealing at low temperatures, allowing for dopant diffusion without damaging flexible substrates, and using different dopant layers for the channel and contact regions to optimize doping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If ion implantation is performed at high temperatures to achieve satisfactory dopant diffusion, then dopant diffusion is improved, but thermal damage to flexible substrates occurs
Solution Approach 1:
The patent changes the temperature parameter from high temperature ion implantation to low temperature processing (below 400°C) combined with excimer laser annealing, achieving both adequate dopant diffusion and prevention of substrate thermal damage
Solution Approach 2:
The patent replaces the mechanical/thermal ion implantation process with a chemical vapor deposition process followed by excimer laser annealing, using photonic energy instead of thermal energy to achieve dopant activation and diffusion
2Manufacturing precision
If conventional high temperature processing is used, then dopant diffusion is achieved, but leak current remains high
Solution Approach 1:
The patent changes the processing temperature parameter to low temperature (below 400°C) and uses excimer laser annealing with specific energy parameters to achieve adequate dopant diffusion while reducing leak current through controlled crystallization
Solution Approach 2:
The patent uses pulsed excimer laser annealing with specific pulse durations and intervals to achieve controlled heating and cooling cycles, enabling dopant diffusion while maintaining low leak current through precise thermal management
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces thermal damage to flexible substrates while achieving effective dopant diffusion and reducing leak currents, enabling the production of high-performance LTPS thin film transistors with improved stability and mobility.
Implementation Method 1
crystallization using excimer laser annealing at low temperatures
Implementation Method 2
crystallizing the amorphous silicon layer to form the polycrystalline silicon active layer
Implementation Method 3
diffusing the dopant from the patterned dopant layer into the substrate by a thermal treatment
Data Source
Figure 1A~1D
Figure 1E~1G
Figure 1H~1J
AI summary
A method of fabricating a polycrystalline silicon thin film transistor is provided. The method includes forming an amorphous silicon layer (aSi) on a base substrate having a pattern corresponding to a polycrystalline silicon active layer (LTPS) of the thin film transistor; the amorphous silicon layer (aSi) has a first region (1) corresponding to a source electrode and a drain electrode contact region in the polycrystalline silicon active layer (LTPS) and a second region (2) corresponding to a channel region in the polycrystalline silicon active layer (LTPS); forming a first dopant layer (CD) on a side of the second region (2) distal to the base substrate; forming a second dopant layer (SDD) on a side of the first region (1) distal to the base substrate; and crystallizing the amorphous silicon layer (aSi), the first dopant layer (CD), and the second dopant layer (SDD) to form the polycrystalline silicon active layer (LTPS). The polycrystalline silicon active layer (LTPS) is doped with a dopant of the first dopant layer (CD) in the second region (2) and doped with a dopant of the second dopant layer (SDD) in the first region (1) during the step of crystallizing the amorphous silicon layer (aSi).