LTPS Array Substrate Mask Reduction via Merged Patterning
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Solution Overview
Problem
Conventional low temperature poly-silicon (LTPS) array substrate manufacturing processes are complex and costly, requiring multiple mask steps, which limits their application to small-sized products due to high production costs and lower yield rates.
Innovation Solution
A simplified manufacturing method for the array substrate involving the use of an amorphous silicon light-shading layer, oxidation to form an insulation film, patterning of semiconductor and metal layers, and reduced mask steps, including doping and etching processes to optimize conductivity and reduce the number of masks needed from ten to seven.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional LTPS manufacturing process with multiple mask steps is used, then manufacturing precision is improved, but device complexity increases and productivity decreases
Solution Approach 1:
The patent combines multiple separate mask processes into a single integrated mask process. Specifically, the source/drain electrode pattern and the semiconductor layer pattern are formed simultaneously through one mask step, eliminating the need for separate masking operations for each layer. This merging approach maintains the required manufacturing precision while significantly reducing process complexity and the total number of mask steps required.
Solution Approach 2:
The single mask used in the invention serves multiple functions: it defines the source/drain electrode patterns, defines the semiconductor layer patterns, and simultaneously creates both structures in one operation. This multi-functional mask approach replaces what would traditionally require multiple specialized masks, reducing device complexity while maintaining manufacturing precision through careful mask design and positioning.
2Manufacturing precision
If conventional LTPS manufacturing process with multiple mask steps is used, then manufacturing precision is improved, but productivity decreases
Solution Approach 1:
By merging the source/drain electrode formation and semiconductor layer formation into a single mask process, the patent reduces the total number of processing steps. This integration maintains the necessary pattern precision through a well-designed single mask while significantly increasing productivity by eliminating multiple sequential mask operations, thereby enhancing production capacity.
3Productivity
If number of mask steps is reduced, then productivity is improved and device complexity is reduced, but manufacturing precision may worsen
Solution Approach 1:
The patent successfully merges multiple patterning functions into one mask process while maintaining manufacturing precision. The single mask is designed with specific features and positioning that enable simultaneous definition of source/drain electrodes and semiconductor layers with the required accuracy. This approach proves that process simplification does not necessarily compromise precision when the merging is done correctly.
Solution Approach 2:
The mask is designed and positioned in advance to account for all subsequent patterning requirements. By performing preliminary planning of the single mask design to incorporate all necessary pattern definitions, the patent ensures that reducing the number of mask steps does not sacrifice manufacturing precision. The preliminary design of the multi-functional mask compensates for the reduced number of correction opportunities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces production costs, and enables the production of larger-sized products by minimizing the complexity and number of mask steps, thereby enhancing the feasibility of LTPS technology for larger displays.
Implementation Method 1
oxidizing the light-shading layer, so as to form an insulation film on the surface of the light-shading layer
Data Source
AI summary
An array substrate and a manufacturing method thereof are provided. The method has steps of: forming a buffer layer, a light-shading layer, and a whole semiconductor layer on a substrate; simultaneously patterning the semiconductor layer and the light-shading layer; and forming a first insulation layer, a first metal layer, a second insulation layer, a second metal layer, a flat layer, and a first transparent conductive layer on the patterned semiconductor layer.