LTPS TFT Gate Insulator Segmentation for Dopant Uniformity
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Solution Overview
Problem
The Low Temperature Poly-Silicon (LTPS) process in manufacturing Thin Film Transistors (TFTs) for Active Matrix Organic Light Emitting Diodes (AMOLEDs results in silicon oxide loss, leading to uneven dopant implantation profiles and electrical properties in source and drain regions, affecting the display quality.
Innovation Solution
A TFT structure and manufacturing method involving a substrate with a buffer layer, semiconductor layer, and specific gate insulating layers, including a silicon oxide layer and a silicon nitride foot with a protrusion, to minimize insulating layer loss and achieve better dopant implantation profiles, using materials like molybdenum and aluminum for the gate electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a photoresist pattern is used as a mask to etch the gate insulating layer, then the gate line and gate electrode can be formed, but silicon oxide loss occurs resulting in uneven dopant implantation profiles
Solution Approach 1:
The gate insulating layer is divided into two segments: a first gate insulating layer (silicon oxide) and a second gate insulating layer foot (silicon nitride). This segmentation allows the etching process to selectively remove only the silicon nitride foot while preserving the silicon oxide layer, preventing silicon oxide loss and ensuring uniform dopant implantation profiles in the source and drain regions.
Solution Approach 2:
The silicon nitride foot acts as an intermediary layer between the photoresist mask and the silicon oxide gate insulating layer. During the etching process, the photoresist pattern removes the silicon nitride foot while the silicon oxide layer remains protected, serving as a mediator that prevents direct contact between the etchant and the silicon oxide, thereby avoiding silicon oxide loss.
2Ease of operation
If the gate insulating layer is etched to form the gate structure, then the gate electrode can be positioned correctly, but the source and drain regions exhibit different electrical properties
Solution Approach 1:
By segmenting the gate insulating layer into a first gate insulating layer and a second gate insulating layer foot, the invention enables precise gate electrode positioning while protecting the first gate insulating layer from etching damage. This ensures that the source and drain regions receive uniform dopant implantation, resulting in consistent electrical properties such as Ion, Ioff, Vth, and mobility across the TFT.
3Ease of manufacture
If the silicon oxide layer is removed during etching, then the gate structure can be formed, but the implantation profiles of source and drain regions become uneven
Solution Approach 1:
The silicon nitride foot serves as an intermediary layer that is selectively removed during etching, allowing gate structure formation while protecting the silicon oxide layer. This intermediary approach ensures that the silicon oxide layer remains intact, providing a uniform surface for dopant implantation in the source and drain regions, thereby achieving uniform implantation profiles.
Solution Approach 2:
The invention applies local quality by creating a second gate insulating layer foot with different material properties (silicon nitride) than the first gate insulating layer (silicon oxide). This local differentiation allows selective etching of the silicon nitride foot while preserving the silicon oxide layer, enabling precise gate structure formation without compromising the uniformity of the implantation profiles.
Data Source
AI summary
The present application provides a thin film transistor, an active matrix organic light emitting diode assembly and a method for manufacturing the same. The thin film transistor includes: a substrate; a buffer layer on the substrate; a semiconductor layer on the buffer layer, including a source region, a drain region and a channel region; a first gate insulating layer covering the semiconductor layer; a second gate insulating layer foot on the first gate insulating layer, a width of the second gate insulating layer foot being smaller than a width of the first gate insulating layer; and a gate electrode on the second gate insulating layer foot; wherein a part of the first gate insulating layer that is on the semiconductor layer has a flat upper surface. The present application may obtain better implantation profiles of source region and drain region, thereby obtaining better uniformity in TFT performance.