LTPS TFT Gate Insulation Planarization for Crystallization
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Solution Overview
Problem
The crystallization effect of amorphous silicon layers in bottom-gate low-temperature polysilicon (LTPS) TFTs is adversely affected by uneven surfaces, leading to unstable properties in the resultant TFTs due to protrusions in the gate insulation layer during excimer laser annealing treatment.
Innovation Solution
A method involving the formation of a gate insulation layer with an even surface by depositing a film thicker than the desired layer and a gate electrode, followed by chemical-mechanical polishing to remove protrusions, ensuring a flat surface for improved crystallization of the amorphous silicon layer, and subsequent patterning and doping to enhance the polysilicon semiconductor layer and electrode contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a gate insulation layer with a protrusion is formed to accommodate the gate electrode, then the gate electrode can be properly positioned, but the amorphous silicon layer becomes uneven and crystallization effect deteriorates
Solution Approach 1:
The gate insulation layer is formed with an excessive thickness that preliminarily covers the gate electrode protrusion. The planarization process then removes the excess material, achieving a flat surface before amorphous silicon layer deposition. This preliminary action prevents surface unevenness from affecting crystallization.
Solution Approach 2:
The protrusion problem is extracted and separated from the gate insulation layer formation process. Instead of forming the gate insulation layer to exactly match the gate electrode height, the solution extracts the excess material through planarization, isolating the positioning function from the surface flatness requirement.
2Reliability
If the gate insulation layer thickness is increased to cover the gate electrode, then proper insulation is achieved, but the surface becomes uneven affecting amorphous silicon layer quality
Solution Approach 1:
The gate insulation layer is formed with excessive thickness that preliminarily ensures adequate insulation coverage over the gate electrode. Subsequent planarization removes the excess, maintaining both insulation performance and surface flatness for high-quality amorphous silicon layer deposition.
Solution Approach 2:
The thickness parameter of the gate insulation layer is changed from an exact-fit value to an excessive value that ensures coverage. The planarization process then adjusts the surface topology parameter, transforming the thick uneven layer into a thin flat layer that maintains insulation while enabling precise amorphous silicon layer formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the crystallization effect and stability of LTPS TFTs by ensuring an even amorphous silicon layer, resulting in enhanced properties and performance.
Implementation Method 1
the protrusion on the gate insulation layer film is removed by chemical-mechanical polishing
Implementation Method 2
subjected to excimer laser annealing (ELA) treatment, so as to form the polysilicon semiconductor layer
Implementation Method 3
crystallizing the amorphous silicon layer, so as to form the polysilicon semiconductor layer
Data Source
AI summary
The present disclosure provides a TFT, its manufacturing method, an array substrate and a display device. The method includes steps of: forming a pattern of a gate electrode on a base substrate; forming a gate insulation layer with an even surface; forming a pattern of a polysilicon semiconductor layer; and forming patterns of a source electrode and a drain electrode. The step of forming the pattern of the polysilicon semiconductor layer includes: crystallizing the amorphous silicon layer, so as to form the polysilicon semiconductor layer.