LTPS TFT Array Substrate Mask Reduction
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Solution Overview
Problem
The current manufacturing process of lower temperature polycrystal silicon (LTPS) TFT array substrates is complex and costly, requiring at least eight masks, which hinders cost reduction and efficiency improvement.
Innovation Solution
A method using four photomasks with specific patterns to define doped regions and metal electrode regions, reducing the number of masks needed and simplifying the process by employing greyscale or halftone photomasks for precise layer formation and ion implantation steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the conventional LTPS TFT manufacturing process is used, then the transistor performance requirements are met, but the process complexity increases and manufacturing cost rises due to requiring at least eight masks
Solution Approach 1:
The patent combines multiple photomask steps into fewer steps by using a single photomask to define both the source/drain electrode patterns and the doped regions through selective ion implantation. The gate electrode pattern and contact hole patterns are also integrated into the same photomask steps, reducing the total mask count from eight to four while maintaining transistor performance requirements.
Solution Approach 2:
The photomask is designed to serve multiple functions simultaneously: defining electrode patterns, defining doped regions through ion implantation windows, and defining contact holes. This multi-functional approach eliminates the need for separate masks for each function, thereby reducing process complexity while meeting performance specifications.
2Manufacturing precision
If the conventional LTPS TFT manufacturing process is used, then the required doped regions and electrodes are formed, but the manufacturing cost increases due to the large number of masks required
Solution Approach 1:
The patent merges the definition of doped regions, electrode patterns, and contact holes into integrated photomask designs. The first photomask defines both source/drain electrodes and their corresponding doped regions in a single step. The second photomask defines gate electrodes and associated doped regions simultaneously, reducing mask count from eight to four while maintaining precise doped region definition.
Solution Approach 2:
The photomasks are designed to pre-define the exact regions that will receive ion implantation, with the mask patterns serving as direct templates for doped region formation. This preliminary patterning approach ensures precise doped region definition while eliminating the need for subsequent separate doping mask steps, thereby reducing manufacturing cost.
3Manufacturing precision
If eight masks are used to form LTPS TFT, then all necessary regions and structures are defined, but the production efficiency decreases and cost increases
Solution Approach 1:
The patent combines multiple patterning and doping operations into four integrated photomask steps. The first photomask step defines source/drain electrodes and their doped regions simultaneously. The second photomask step defines gate electrodes and channel doped regions in one operation. Contact holes are defined in the third photomask step, and the fourth step completes the electrode interconnections. This merging approach maintains region definition accuracy while doubling production efficiency by halving the mask step count from eight to four.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces production costs and improves efficiency by minimizing the number of photomasks required, enhancing the manufacturing process for LTPS TFT array substrates.
Implementation Method 1
defining a heavily doped region of a source electrode of an N-channel area, a lightly doped region of the source electrode of the N-channel area, a heavily doped region of a drain electrode of the N-channel area and a lightly doped region of the drain electrode of the N-channel area by using a first photomask having a first pattern
Data Source
AI summary
The present invention discloses a method of manufacturing array substrate, comprising: A) defining a heavily doped region and a lightly doped region of a source electrode of an N-channel area, and a heavily doped region and a lightly doped region of a drain electrode of the N-channel area by using a first photomask having a first pattern; B) defining a doped region of a source electrode of a P-channel area and a doped region of a drain electrode of the P-channel area by using a second photomask having a second pattern; C) defining a pixel region, a contact hole region by using a third photomask having a third pattern; and D) defining a metal electrode region by using a fourth photomask having a fourth pattern.