LTPS TFT Gate Electrode Region Segmentation for Leak Current Suppression
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional top gate TFT elements using low-temperature polycrystalline silicon (LTPS) face issues with varying conduction current or on-resistance in the conductive state and leak current in the non-conductive state, particularly due to the gate electrode crossing the semiconductor layer, which affects the performance and efficiency of display devices.
Innovation Solution
The proposed solution involves a display device structure with a polycrystalline semiconductor layer, a gate insulating film, and a gate electrode, where the semiconductor layer is divided into regions with specific impurity diffusion regions to control the electric field and prevent leak current, including a first region overlapping with the gate electrode, and second and third regions that sandwich the first region, with the second and third regions acting as source and drain, respectively, and having impurity diffusion regions that prevent leak current by extending along the gate electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate electrode crosses the semiconductor layer in the top gate TFT element using LTPS, then the manufacturing process is simplified, but the conduction current varies and leak current increases
Solution Approach 1:
The semiconductor layer is divided into a first region (overlapping with gate electrode) and second and third regions (sandwiching the first region), with impurity diffusion regions formed in the second and third regions to create barrier effects that prevent leak current while maintaining manufacturing simplicity
Solution Approach 2:
Impurity diffusion regions are selectively formed in the second and third regions of the semiconductor layer, creating localized barrier regions that prevent leak current at critical interfaces without affecting the overall device structure or manufacturing process
2Ease of manufacture
If the gate electrode crosses the semiconductor layer in the top gate TFT element using LTPS, then the manufacturing process is simplified, but the on-resistance varies
Solution Approach 1:
The semiconductor layer is segmented into distinct regions with controlled impurity diffusion, creating barrier regions that stabilize on-resistance while preserving the simplified top gate manufacturing process
Solution Approach 2:
Impurity concentration is changed locally in the second and third regions through selective diffusion, creating barrier regions that control and stabilize on-resistance without altering the overall device architecture
3Reliability
If methods changing the two-dimensional shape of the TFT element are used to prevent leak current, then leak current is reduced, but the circuit area increases
Solution Approach 1:
Instead of changing the overall two-dimensional shape of the TFT element, impurity diffusion regions are locally formed in the second and third regions to create barrier effects, maintaining compact circuit area while suppressing leak current
Solution Approach 2:
Impurity diffusion regions act as intermediary barrier regions between the source/drain and the gate electrode, preventing leak current without requiring geometric modifications that would increase circuit area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses leak current and reduces variation in conduction current or on-resistance without increasing the circuit area, thereby enhancing the performance and reliability of display devices.
Implementation Method 1
the second and third regions acting as source and drain, respectively, and having impurity diffusion regions that prevent leak current by extending along the gate electrode
Implementation Method 2
the gate electrode is formed above the polycrystalline semiconductor layer through the gate insulating film
Data Source
AI summary
The gate electrode is formed above the polycrystalline semiconductor layer through the gate insulating film. The polycrystalline semiconductor layer includes a first region overlapping with the gate electrode in plan view. The first region is sandwiched between the second region and the third region. The second region of the polycrystalline semiconductor layer includes a first impurity diffusion region and two second impurity diffusion regions opposite in conductivity type to the first impurity diffusion region. The first region and the first impurity diffusion region are in contact with each other at a first boundary. The first region and the two second impurity diffusion regions are in contact with each other at second boundaries. The two second impurity diffusion regions sandwiching the first impurity diffusion region are provided along the gate electrode. Thus, a leak current is suppressed.