LTPS TFT Array Substrate Single Patterning Process
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The manufacturing process of LTPS TFT array substrates is complex and requires multiple patterning processes, leading to low productivity and high alignment accuracy issues, which result in reduced yield due to alignment errors.
Innovation Solution
A simplified method involving fewer patterning processes, where a pattern of an active layer and gate insulating layer is formed on a base substrate, followed by a single patterning process to create gate, source, and drain electrodes, and data lines, with a passivation layer to expose contact holes for electrical connections, reducing the number of steps and improving alignment accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple patterning processes are used to form gate electrodes, source electrodes, drain electrodes, and data lines separately, then the manufacturing precision and alignment accuracy are improved, but the device complexity and manufacturing time increase significantly
Solution Approach 1:
The patent combines the formation of gate electrodes, source electrodes, drain electrodes, and data lines into a single patterning process. A metal layer is deposited and then patterned in one step to create all these conductive structures simultaneously, eliminating the need for multiple separate patterning operations and their associated alignment requirements.
Solution Approach 2:
The single patterning process creates multiple functional conductive structures (gate electrodes, source electrodes, drain electrodes, and data lines) from one patterned metal layer. This multi-functional approach allows one patterning step to serve the purpose of what would traditionally require four or more separate patterning steps.
2Manufacturing precision
If multiple patterning processes are used to form various electrodes and lines, then the manufacturing precision is improved, but the productivity decreases due to increased manufacturing time
Solution Approach 1:
The patent merges multiple sequential patterning operations into a single patterning step, directly reducing the total manufacturing time and process count while maintaining the necessary structural precision through the unified pattern formation approach.
3Manufacturing precision
If multiple patterning processes are used with photoresist masks, then the manufacturing precision is improved, but the loss of time for mask application and removal increases
Solution Approach 1:
The patent eliminates the need for multiple photoresist mask applications and removals by using a single patterning process. This reduces the cumulative time spent on photoresist processing while maintaining pattern accuracy through the consolidated approach.
Data Source
AI summary
An array substrate, a manufacturing method thereof, a display device, a thin-film transistor (TFT) and a manufacturing method thereof are disclosed. The method for manufacturing the TFT comprises: forming a pattern of an active layer and a gate insulating layer provided with a metal film on a base substrate; patterning the metal film by one patterning process, and forming patterns of a gate electrode, a source electrode, a drain electrode, a gate line and a data line; forming a passivation layer on the base substrate; patterning the passivation layer by one patterning process, and forming a source contact hole, a drain contact hole and a bridge structure contact hole; and forming a transparent conductive film on the base substrate, and removing partial transparent conductive film to form a source contact portion, a drain contact portion (214), a pixel electrode and a bridge structure. The manufacturing method can reduce the number of the patterning processes.