Lookup Table Adder Circuit for Faster FPGA Carry Selection
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Solution Overview
Problem
Field-programmable gate arrays (FPGAs) face challenges in efficiently implementing large adders due to sequential time delays, which hinder performance in applications like neural networks that require numerous additions, and existing solutions increase circuit complexity or require additional logic blocks.
Innovation Solution
The design modifies lookup tables (LUTs) to function as both traditional LUTs and adders, using multiplexers to determine and select carry outputs efficiently, allowing for the creation of adder slices that can operate as 1-bit or 2-bit adders without additional logic blocks, enabling more dense packing on a single chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If 1-bit adders are chained sequentially to create larger adders, then the adder can be constructed using simple 1-bit adder units, but the time delay increases linearly with the number of bits
Solution Approach 1:
The patent pre-computes both possible sum outputs (one for carry-in=0 and one for carry-in=1) before the actual carry input is known. These preliminary results are stored in lookup tables, and when the carry input arrives, the correct pre-computed result is immediately selected via a multiplexer, eliminating the sequential waiting time inherent in traditional ripple-carry adders.
2Loss of time
If carry-select adder design is used to reduce time delay, then the addition speed increases significantly, but the circuit complexity increases due to additional logic blocks
Solution Approach 1:
The patent makes the lookup tables multi-functional by configuring them to store adder results dynamically. The same LUT infrastructure that normally implements logic functions is repurposed to store pre-computed addition results, eliminating the need for dedicated carry-select adder logic blocks while achieving the same time delay reduction.
Solution Approach 2:
The patent merges the LUT functionality with the adder functionality. Instead of having separate LUTs and separate adder logic blocks, the design combines them so that the LUTs themselves perform the adder function by storing and selecting appropriate sum and carry outputs based on input operands and carry-in signals.
3Adaptability or versatility
If traditional LUTs are used for addition operations, then the FPGA maintains flexibility for various logic functions, but the addition operations consume more time and power
Solution Approach 1:
The patent introduces dynamic reconfiguration capability where the LUTs can switch between their traditional logic function mode and their adder mode. The LUTs are configured at runtime based on whether addition or general logic function is required, allowing the FPGA to optimize performance for arithmetic operations while maintaining full programming flexibility for other applications.
Data Source
AI summary
A four-input lookup table (“LUT4”) is modified to operate in a first mode as an ordinary LUT4 and in a second mode as a 1-bit adder providing a sum output and a carry output. A six-input lookup table (“LUT6”) is modified to operate in a first mode as an ordinary LUT6 with a single output and in a second mode as a 2-bit adder providing a sum output and a carry output. Both possible results for the two different possible carry inputs can be determined and selected between when the carry input is available, implementing a 2-bit carry-select adder when in the second mode and retaining the ability to operate as an ordinary LUT6 in the first mode. Using the novel LUT6 design in a circuit chip fabric allows a 2-bit adder slice to be built that efficiently makes use of the LUT6 without requiring additional logic blocks.