LUT-Based Focused Ion Beam Fill-Cell Design
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Solution Overview
Problem
Post-silicon stage editing of integrated circuits using FIB techniques is limited in flexibility and often requires destructive methods, making it difficult to add or alter logical functions without resorting to metal respin and mask changes, which is costly and time-consuming.
Innovation Solution
Incorporating configurable multiplexer-based lookup tables (LUTs) in white spaces of the integrated circuit die, which can be configured using FIB to connect into the existing logic network, allowing for non-destructive addition of logical functions and bug fixes without altering metal interconnect masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FIB techniques are used for post-silicon editing, then circuit debugging and optimization can be performed on live devices, but the editing flexibility is limited and the process is destructive by nature
Solution Approach 1:
The patent applies preliminary action by pre-configuring LUTs with multiple possible logic functions before the FIB editing process. The LUTs are designed with selectable inputs that can be configured to implement different logic functions (AND, OR, XOR, etc.) through FIB-directed connections, allowing flexible post-silicon editing without destructive methods.
Solution Approach 2:
The patent uses LUTs as intermediary elements between existing circuit logic and the FIB editing process. These LUTs serve as reconfigurable mediators that can be programmed via FIB to implement various logic functions, enabling flexible circuit modification without directly altering the underlying metal interconnect masks.
2Device complexity
If simple reconnection is performed via FIB, then editing can be completed with minimal complexity, but adding logical functions to repair or alter existing logic is seldom successful
Solution Approach 1:
The patent implements universality by designing LUTs that can perform multiple logic functions (AND, OR, XOR, NAND, NOR, etc.) depending on their configuration. Each LUT serves as a universal logic element that can be programmed via FIB to implement any desired logic function, allowing a single structure to replace multiple specialized logic gates.
Solution Approach 2:
The patent applies dynamics by making the LUT configuration changeable after fabrication. The select inputs of the LUTs can be dynamically reconfigured through FIB editing to alter the logic function implemented, enabling the circuit to adapt and correct various logic errors without requiring physical replacement of components.
3Reliability
If metal respin and mask changes are performed to add logic cells, then functional bugs can be corrected, but the process is costly and time-consuming
Solution Approach 1:
The patent uses LUTs as programmable copies of logic functions that can be configured to implement different behaviors. Instead of physically respinning metal layers to add logic cells, the LUTs provide a software-like configuration layer that can be programmed via FIB to replicate desired logic functions, avoiding the time-consuming mask fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables flexible and cost-effective post-silicon logic modifications by allowing functional changes to be confirmed and implemented directly on the silicon without the need for metal respin or new mask fabrication, reducing the complexity and expense of bug fixes.
Implementation Method 1
The high-energy Ga+ ion beam can mill through conductors
Implementation Method 2
various types of gases can be used to either enhance milling precision or more effectively deposit conductive and dielectric materials
Data Source
AI summary
An integrated circuit includes a plurality of logic function circuits disposed on the integrated circuit and interconnected by metal interconnect lines to form a logic network. A plurality of configurable logic function circuits is also disposed on the integrated circuit, each configurable logic function circuit being disposed on a respective area on the integrated circuit and not interconnected by the metal interconnect lines to form the logic network.