Cascaded LUT Carry Logic for Carry Chain Initialization
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Solution Overview
Problem
Existing programmable integrated circuits, such as FPGAs, face inefficiencies in implementing carry logic due to the need for separate outputs for sum and carry signals, which increases output multiplexer size and complexity, and limits carry chain initialization and packing efficiency.
Innovation Solution
A cascaded lookup-table (LUT) carry logic circuit is introduced, where each LUT includes sum and carry logic, and cascade multiplexers are used to couple the carry output from one LUT to the input of another, allowing direct provision of sum and carry outputs and enabling carry chain initialization at every LUT, thus reducing output multiplexer size and enhancing carry chain packing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If separate outputs are used for sum and carry signals in traditional LUT configurations, then the logic function can be implemented, but the output multiplexer size and complexity increase
Solution Approach 1:
The patent combines sum and carry outputs into a single multiplexer by encoding them together. The carry logic output is multiplexed to an input of the second LUT, and both sum and carry are provided through shared output paths, reducing the number of separate multiplexers needed and simplifying the overall output structure.
Solution Approach 2:
The multiplexer is designed to handle multiple functions: it routes both sum and carry signals, supports carry chain initialization, and enables direct LUT-to-LUT connections. This multi-functional design reduces the need for dedicated separate multiplexers for each function.
2Productivity
If traditional separate carry logic is used, then carry functions can be implemented, but carry chain initialization and packing efficiency are limited
Solution Approach 1:
The carry logic output is pre-configured and multiplexed to an input of the second LUT before the addition operation completes. This preliminary setup enables carry chains to be initialized at every LUT boundary, allowing efficient packing and propagation without waiting for intermediate stages to complete.
Solution Approach 2:
The carry chain is segmented into discrete units that can be independently initialized at each LUT. The multiplexer structure allows each LUT to serve as a potential carry chain start point, enabling flexible packing arrangements that can be adapted to different design requirements.
3Speed
If direct LUT-to-LUT connections are implemented, then connection speed improves, but output multiplexer requirements increase
Solution Approach 1:
The patent merges the carry output path with the sum output path by using a shared multiplexer structure. The carry logic output is multiplexed to an input of the second LUT, allowing direct connections without requiring separate dedicated multiplexers for carry signals, thus maintaining speed while reducing complexity.
Data Source
AI summary
In an example, a configurable logic element for a programmable integrated circuit (IC) includes a first lookup-table (LUT) including first inputs and first outputs, and first sum logic and first carry logic coupled between the first inputs and the first outputs; a second LUT including second inputs and second outputs, and second sum logic coupled between the second inputs and the second outputs; and first and second cascade multiplexers respectively coupled to the first and second LUTs, an input of the second cascade multiplexer coupled to an output of the first carry logic in the first LUT.