LUT Cascading Circuit for Wide FPGA Logic With Less Interconnect
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Solution Overview
Problem
The use of programmable interconnects in FPGAs for LUT-to-LUT connections is resource-intensive and affects performance, as it requires a large number of interconnect lines and points, making it expensive in terms of resource usage and performance for implementing large combinatorial functions.
Innovation Solution
A lookup-table (LUT) cascading circuit is introduced, where multiple LUTs are coupled through a common set of input terminals, multiplexers, and cascading multiplexers, allowing LUTs to be chained together without relying on programmable interconnects, enabling efficient LUT-to-LUT connections and implementation of wide combinatorial functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If programmable interconnects are used for LUT-to-LUT connections, then LUTs can be connected to implement large combinatorial functions, but resource usage increases and performance deteriorates
Solution Approach 1:
The patent merges the interconnect function with the LUT structure by introducing cascading inputs directly integrated into the LUT logic. Multiple LUTs share common input terminals and use cascading multiplexers to select between local inputs and cascaded inputs, eliminating the need for separate programmable interconnect resources between adjacent LUTs.
Solution Approach 2:
The cascading multiplexer acts as an intermediary element that mediates between the LUT logic and external inputs. It selects between signals from common input terminals and cascaded signals from other LUTs, providing a localized routing mechanism that replaces the need for global programmable interconnect.
2Adaptability or versatility
If programmable interconnects are used for LUT-to-LUT connections, then LUTs can be connected to implement large combinatorial functions, but performance decreases due to increased delay
Solution Approach 1:
The patent segments the signal routing path into local and global components. Cascading connections between adjacent LUTs use direct local routing through shared input terminals and cascading multiplexers, while programmable interconnect is reserved for longer-distance connections. This segmentation minimizes the delay for frequent LUT-to-LUT operations.
Solution Approach 2:
The cascading input paths are pre-established through shared input terminals and dedicated cascading multiplexers, eliminating the need for dynamic routing setup. This preliminary preparation of connection paths reduces setup time and ensures consistent, predictable delay characteristics for cascaded LUT operations.
Data Source
AI summary
In an example, a LUT for a programmable integrated circuit (IC) includes a plurality of input terminals, and a cascading input coupled to at least one other LUT in the programmable IC. The LUT further includes LUT logic having a plurality of LUTs each coupled to a common set of the input terminals. The LUT further includes a plurality of multiplexers having inputs coupled to outputs of the plurality of LUTs, and an output multiplexer having inputs coupled to outputs of the plurality of multiplexers. The LUT further includes a plurality of cascading multiplexers each having an output coupled to a control input of a respective one of the plurality of multiplexers, each of the plurality of cascading multiplexers comprising a plurality of inputs, at least one of the plurality of inputs coupled to the cascading input.