LUT-Based Chiplet Encryption via Dynamic XOR and CRC Verification
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Solution Overview
Problem
There is a need for secure lightweight chiplet-to-chiplet communication in resource-constrained devices that minimizes the use of resource-intensive operations and supports verification of message integrity and authenticity without relying on expensive hash functions.
Innovation Solution
The implementation of dynamic substitution boxes (LUTs) and keystream tables (KSTs) for encryption and decryption, using XOR operations, along with lightweight CRC for verification, which are computationally efficient and reduce the need for multiplication operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional hash functions are used for message verification, then verification security is improved, but computational cost increases
Solution Approach 1:
The patent replaces expensive hash functions with a cheaper verification mechanism using CRC (Cyclic Redundancy Check) and XOR operations. This disposable approach uses simple mathematical operations that are computationally inexpensive while still providing adequate verification security for resource-constrained devices.
Solution Approach 2:
The patent substitutes complex cryptographic hash functions with simpler mathematical operations including CRC calculations and XOR operations. This replacement reduces computational complexity from O(n) or higher to O(1) for the core verification operations, making it suitable for resource-constrained environments.
2Reliability
If resource-intensive encryption operations are used, then security is improved, but device performance deteriorates
Solution Approach 1:
The patent employs dynamic substitution boxes (S-boxes) that are generated on-the-fly during encryption/decryption operations rather than using static pre-defined tables. This dynamic approach reduces memory access requirements and allows the system to adapt to different operational conditions, improving performance while maintaining security.
Solution Approach 2:
The patent changes the operational parameters of the encryption system by using lightweight cryptographic primitives with simplified algebraic structures. The system uses operations in finite fields with smaller dimensions and simpler group operations, reducing computational complexity while maintaining adequate security margins for resource-constrained applications.
3Use of energy by moving object
If lightweight encryption protocols are used, then resource consumption is reduced, but verification capability is weakened
Solution Approach 1:
The patent segments the verification process into two distinct components: (1) CRC-based integrity checking for detecting accidental corruption, and (2) XOR-based authentication tags for detecting intentional tampering. This segmentation allows each component to be optimized independently, maintaining verification capability while reducing overall resource consumption.
Solution Approach 2:
The patent creates a composite verification mechanism that combines CRC (Cyclic Redundancy Check) with XOR-based authentication tags. This composite approach layers multiple verification techniques together, where CRC provides bulk integrity checking and XOR tags provide targeted authentication, achieving robust verification with reduced computational overhead compared to using a single comprehensive hash function.
Data Source
AI summary
A cryptographic method includes (1) with the first chiplet, parsing a message into one or more message blocks (2) dynamically generating a first target value that is associated with a first key (3) dynamically generating a second target value that is associated with a second key (4) encrypting at least one message block of the at least one or more message blocks to generate some ciphertext, the encryption being performed with at least one operation that includes at least one XOR operation, the at least one XOR operation performed at least in part with the first target value and with at least the second target value, the first target value and the second target value being accessed via the first and second keys, respectively; and (5) with at least one processing device associated with the first chiplet, transmitting the some ciphertext to a second chiplet.