Hierarchical LUT Distribution Matching Circuit
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Solution Overview
Problem
Existing distribution matching and dematching circuits require large scales and slow execution speeds due to the need for multiple integer multiplications and additions, necessitating large arithmetic circuits and parallel implementation.
Innovation Solution
The use of a hierarchical tree structure of lookup tables in distribution matching and dematching circuits, where upper-level tables convert input information into designation information, and lower-level tables output signal point information, reducing the need for sequential integer operations and parallel arithmetic circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple integer multiplications and additions are performed in distribution matching and dematching, then the processing accuracy is improved, but the circuit scale increases and execution speed decreases
Solution Approach 1:
The patent divides the distribution matching and dematching process into multiple stages, each handling a portion of the integer multiplications and additions. By segmenting the computational tasks across different circuit modules operating in parallel, the patent maintains processing accuracy while reducing the complexity of any single circuit unit and improving overall execution speed.
2Measurement precision
If multiple integer multiplications and additions are performed in distribution matching and dematching, then the processing accuracy is improved, but the execution speed decreases
Solution Approach 1:
The patent segments the computational process into multiple parallel stages, where each stage performs a subset of the required integer multiplications and additions. This segmentation enables concurrent execution of multiple operations, thereby maintaining processing accuracy while significantly improving execution speed.
Solution Approach 2:
The patent employs dynamic circuit configurations that can adaptively allocate computational resources based on the specific processing requirements. By dynamically reconfiguring the circuit to perform operations in parallel when possible and sequentially when necessary, the patent optimizes execution speed while preserving processing accuracy.
3Speed
If parallel arithmetic circuits are implemented to reduce processing delay, then the execution speed is improved, but the circuit scale becomes very large
Solution Approach 1:
The patent divides the parallel arithmetic circuits into multiple smaller functional units that operate in a pipelined manner. Each unit handles a specific portion of the computation, allowing parallel processing to be achieved while keeping the scale of individual circuit components manageable through systematic segmentation of the overall computational task.
Data Source
AI summary
In a distribution matching circuit, output data of a plurality of LUTs forming a hierarchical tree structure sequentially designates a combination of signal point groups in a signal space managed by an LUT in an immediately lower level, and signal point information after distribution matching is output for each LUT in the lowermost level.